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board: Add support for Arduino Portenta H7 #1909

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0c22ea7
add initial source files for M7/M4 machine and runtime support
ardnew May 10, 2021
73dc97c
working dual-core blinky with new example
ardnew May 27, 2021
fdc37c6
add PinMode wrapper to support 8-bit type in machine.go
ardnew May 28, 2021
80660fa
fix length of Cortex-M7 flash region
ardnew May 28, 2021
386b388
integrate with latest STM32 SVD register descriptions
ardnew May 28, 2021
fa21716
update target linker script names
ardnew May 28, 2021
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169 changes: 169 additions & 0 deletions src/device/stm32/stm32h7x5_cm7_scb.go
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// Hand created file. DO NOT DELETE.
// Type definitions, fields, and constants associated with the SCB peripheral of
// the STM32H7x5 family of dual-core MCUs.
// These definitions are applicable to the Cortex-M7 core only.

// +build stm32h7x5_cm7

package stm32

import (
"device/arm"
"runtime/volatile"
"unsafe"
)

// SCB registers that were not automatically exported in the target SVD.
var (
SCB_SHCSR = (*volatile.Register32)(unsafe.Pointer((uintptr(unsafe.Pointer(SCB)) + 0x024))) // Offset: 0x024 (R/W) System Handler Control and State Register
SCB_CCSIDR = (*volatile.Register32)(unsafe.Pointer((uintptr(unsafe.Pointer(SCB)) + 0x080))) // Offset: 0x080 (R/ ) Cache Size ID Register
SCB_CSSELR = (*volatile.Register32)(unsafe.Pointer((uintptr(unsafe.Pointer(SCB)) + 0x084))) // Offset: 0x084 (R/W) Cache Size Selection Register
SCB_ICIALLU = (*volatile.Register32)(unsafe.Pointer((uintptr(unsafe.Pointer(SCB)) + 0x250))) // Offset: 0x250 ( /W) I-Cache Invalidate All to PoU
SCB_DCISW = (*volatile.Register32)(unsafe.Pointer((uintptr(unsafe.Pointer(SCB)) + 0x260))) // Offset: 0x260 ( /W) D-Cache Invalidate by Set-way
SCB_DCCISW = (*volatile.Register32)(unsafe.Pointer((uintptr(unsafe.Pointer(SCB)) + 0x274))) // Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way
)

func EnableICache(enable bool) {
if enable == arm.SCB.CCR.HasBits(SCB_CCR_ICACHEEN_Msk) {
return
}
if enable {
arm.AsmFull(`
dsb 0xF
isb 0xF
`, nil)
SCB_ICIALLU.Set(0)
arm.AsmFull(`
dsb 0xF
isb 0xF
`, nil)
arm.SCB.CCR.SetBits(SCB_CCR_ICACHEEN_Msk)
arm.AsmFull(`
dsb 0xF
isb 0xF
`, nil)
} else {
arm.AsmFull(`
dsb 0xF
isb 0xF
`, nil)
arm.SCB.CCR.ClearBits(SCB_CCR_ICACHEEN_Msk)
SCB_ICIALLU.Set(0)
arm.AsmFull(`
dsb 0xF
isb 0xF
`, nil)
}
}

var (
scbDcci volatile.Register32
scbSets volatile.Register32
scbWays volatile.Register32
)

func EnableDCache(enable bool) {
if enable == arm.SCB.CCR.HasBits(SCB_CCR_DCACHEEN_Msk) {
return
}
if enable {
SCB_CSSELR.Set(0)
arm.AsmFull(`
dsb 0xF
`, nil)
scbDcci.Set(SCB_CCSIDR.Get())
scbSets.Set((scbDcci.Get() & SCB_DCCISW_NUMSETS_Msk) >> SCB_DCCISW_NUMSETS_Pos)
for scbSets.Get() != 0 {
scbWays.Set((scbDcci.Get() & SCB_DCCISW_ASSOC_Msk) >> SCB_DCCISW_ASSOC_Pos)
for scbWays.Get() != 0 {
SCB_DCISW.Set(((scbSets.Get() << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
((scbWays.Get() << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk))
scbWays.Set(scbWays.Get() - 1)
}
scbSets.Set(scbSets.Get() - 1)
}
arm.AsmFull(`
dsb 0xF
`, nil)
arm.SCB.CCR.SetBits(SCB_CCR_DCACHEEN_Msk)
arm.AsmFull(`
dsb 0xF
isb 0xF
`, nil)
} else {
var ()
SCB_CSSELR.Set(0)
arm.AsmFull(`
dsb 0xF
`, nil)
arm.SCB.CCR.ClearBits(SCB_CCR_DCACHEEN_Msk)
arm.AsmFull(`
dsb 0xF
`, nil)
scbDcci.Set(SCB_CCSIDR.Get())
scbSets.Set((scbDcci.Get() & SCB_DCCISW_NUMSETS_Msk) >> SCB_DCCISW_NUMSETS_Pos)
for scbSets.Get() != 0 {
scbWays.Set((scbDcci.Get() & SCB_DCCISW_ASSOC_Msk) >> SCB_DCCISW_ASSOC_Pos)
for scbWays.Get() != 0 {
SCB_DCCISW.Set(((scbSets.Get() << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
((scbWays.Get() << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk))
scbWays.Set(scbWays.Get() - 1)
}
scbSets.Set(scbSets.Get() - 1)
}
arm.AsmFull(`
dsb 0xF
isb 0xF
`, nil)
}
}

const (
SCB_CCR_ICACHEEN_Pos = 17 // SCB CCR: IC Position
SCB_CCR_ICACHEEN_Msk = (1 << SCB_CCR_ICACHEEN_Pos) // SCB CCR: IC Mask
SCB_CCR_DCACHEEN_Pos = 16 // SCB CCR: DC Position
SCB_CCR_DCACHEEN_Msk = (1 << SCB_CCR_DCACHEEN_Pos) // SCB CCR: DC Mask

SCB_DCISW_WAY_Pos = 30 // SCB DCISW: WAY Position
SCB_DCISW_WAY_Msk = 3 << SCB_DCISW_WAY_Pos // SCB DCISW: WAY Mask
SCB_DCISW_SET_Pos = 5 // SCB DCISW: SET Position
SCB_DCISW_SET_Msk = 0x1FF << SCB_DCISW_SET_Pos // SCB DCISW: SET Mask

SCB_DCCISW_WAY_Pos = 30 // SCB DCCISW: WAY Position
SCB_DCCISW_WAY_Msk = 3 << SCB_DCCISW_WAY_Pos // SCB DCCISW: WAY Mask
SCB_DCCISW_SET_Pos = 5 // SCB DCCISW: SET Position
SCB_DCCISW_SET_Msk = 0x1FF << SCB_DCCISW_SET_Pos // SCB DCCISW: SET Mask
SCB_DCCISW_ASSOC_Pos = 0x3 // SCB DCCISW: ASSOCIATIVITY Position
SCB_DCCISW_ASSOC_Msk = 0x1FF8 // SCB DCCISW: ASSOCIATIVITY Mask
SCB_DCCISW_NUMSETS_Pos = 0xD // SCB DCCISW: NUMSETS Position
SCB_DCCISW_NUMSETS_Msk = 0xFFFE000 // SCB DCCISW: NUMSETS Mask

SCB_SHCSR_USGFAULTENA_Pos = 18 // SCB SHCSR: USGFAULTENA Position
SCB_SHCSR_USGFAULTENA_Msk = 1 << SCB_SHCSR_USGFAULTENA_Pos // SCB SHCSR: USGFAULTENA Mask
SCB_SHCSR_BUSFAULTENA_Pos = 17 // SCB SHCSR: BUSFAULTENA Position
SCB_SHCSR_BUSFAULTENA_Msk = 1 << SCB_SHCSR_BUSFAULTENA_Pos // SCB SHCSR: BUSFAULTENA Mask
SCB_SHCSR_MEMFAULTENA_Pos = 16 // SCB SHCSR: MEMFAULTENA Position
SCB_SHCSR_MEMFAULTENA_Msk = 1 << SCB_SHCSR_MEMFAULTENA_Pos // SCB SHCSR: MEMFAULTENA Mask
SCB_SHCSR_SVCALLPENDED_Pos = 15 // SCB SHCSR: SVCALLPENDED Position
SCB_SHCSR_SVCALLPENDED_Msk = 1 << SCB_SHCSR_SVCALLPENDED_Pos // SCB SHCSR: SVCALLPENDED Mask
SCB_SHCSR_BUSFAULTPENDED_Pos = 14 // SCB SHCSR: BUSFAULTPENDED Position
SCB_SHCSR_BUSFAULTPENDED_Msk = 1 << SCB_SHCSR_BUSFAULTPENDED_Pos // SCB SHCSR: BUSFAULTPENDED Mask
SCB_SHCSR_MEMFAULTPENDED_Pos = 13 // SCB SHCSR: MEMFAULTPENDED Position
SCB_SHCSR_MEMFAULTPENDED_Msk = 1 << SCB_SHCSR_MEMFAULTPENDED_Pos // SCB SHCSR: MEMFAULTPENDED Mask
SCB_SHCSR_USGFAULTPENDED_Pos = 12 // SCB SHCSR: USGFAULTPENDED Position
SCB_SHCSR_USGFAULTPENDED_Msk = 1 << SCB_SHCSR_USGFAULTPENDED_Pos // SCB SHCSR: USGFAULTPENDED Mask
SCB_SHCSR_SYSTICKACT_Pos = 11 // SCB SHCSR: SYSTICKACT Position
SCB_SHCSR_SYSTICKACT_Msk = 1 << SCB_SHCSR_SYSTICKACT_Pos // SCB SHCSR: SYSTICKACT Mask
SCB_SHCSR_PENDSVACT_Pos = 10 // SCB SHCSR: PENDSVACT Position
SCB_SHCSR_PENDSVACT_Msk = 1 << SCB_SHCSR_PENDSVACT_Pos // SCB SHCSR: PENDSVACT Mask
SCB_SHCSR_MONITORACT_Pos = 8 // SCB SHCSR: MONITORACT Position
SCB_SHCSR_MONITORACT_Msk = 1 << SCB_SHCSR_MONITORACT_Pos // SCB SHCSR: MONITORACT Mask
SCB_SHCSR_SVCALLACT_Pos = 7 // SCB SHCSR: SVCALLACT Position
SCB_SHCSR_SVCALLACT_Msk = 1 << SCB_SHCSR_SVCALLACT_Pos // SCB SHCSR: SVCALLACT Mask
SCB_SHCSR_USGFAULTACT_Pos = 3 // SCB SHCSR: USGFAULTACT Position
SCB_SHCSR_USGFAULTACT_Msk = 1 << SCB_SHCSR_USGFAULTACT_Pos // SCB SHCSR: USGFAULTACT Mask
SCB_SHCSR_BUSFAULTACT_Pos = 1 // SCB SHCSR: BUSFAULTACT Position
SCB_SHCSR_BUSFAULTACT_Msk = 1 << SCB_SHCSR_BUSFAULTACT_Pos // SCB SHCSR: BUSFAULTACT Mask
SCB_SHCSR_MEMFAULTACT_Pos = 0 // SCB SHCSR: MEMFAULTACT Position
SCB_SHCSR_MEMFAULTACT_Msk = 1 << SCB_SHCSR_MEMFAULTACT_Pos // SCB SHCSR: MEMFAULTACT Mask
)
177 changes: 177 additions & 0 deletions src/device/stm32/stm32h7x5_cmx_hsem.go
View file
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Original file line number Diff line number Diff line change
@@ -0,0 +1,177 @@
// Hand created file. DO NOT DELETE.
// Type definitions, fields, and constants associated with the HSEM peripheral
// of the STM32H7x5 family of dual-core MCUs.
// These definitions are applicable to both the Cortex-M7 and Cortex-M4 cores.

// +build stm32h7x5

package stm32

import (
"runtime/volatile"
"unsafe"
)

var (
HSEM_CORE1 = (*HSEM_CORE_Type)(unsafe.Pointer((uintptr(unsafe.Pointer(HSEM)) + 0x100)))
HSEM_CORE2 = (*HSEM_CORE_Type)(unsafe.Pointer((uintptr(unsafe.Pointer(HSEM)) + 0x110)))
)

// HSEM_CORE
type HSEM_CORE_Type struct {
IER volatile.Register32 // HSEM Interrupt enable register Address offset: HSEM + 1N0h (Interrupt N (0 or 1))
ICR volatile.Register32 // HSEM Interrupt clear register Address offset: HSEM + 1N4h (Interrupt N (0 or 1))
ISR volatile.Register32 // HSEM Interrupt Status register Address offset: HSEM + 1N8h (Interrupt N (0 or 1))
MISR volatile.Register32 // HSEM Interrupt Masked Status register Address offset: HSEM + 1NCh (Interrupt N (0 or 1))
}

type HSEM_ID_Type uint8

// Lock performs a 1-step (read) lock on the receiver semaphore ID.
// Semaphores can be used to ensure synchronization between processes running on
// different cores. Lock provides a non-blocking mechanism to lock semaphores
// in an atomic way.
// Returns true if and only if the semaphore lock is acquired or the given core
// already has the semaphore locked.
func (id HSEM_ID_Type) Lock(core uint32) bool {
switch id {
case 0:
return HSEM.RLR0.Get() == (HSEM_RLR0_LOCK | core)
case 1:
return HSEM.RLR1.Get() == (HSEM_RLR1_LOCK | core)
case 2:
return HSEM.RLR2.Get() == (HSEM_RLR2_LOCK | core)
case 3:
return HSEM.RLR3.Get() == (HSEM_RLR3_LOCK | core)
case 4:
return HSEM.RLR4.Get() == (HSEM_RLR4_LOCK | core)
case 5:
return HSEM.RLR5.Get() == (HSEM_RLR5_LOCK | core)
case 6:
return HSEM.RLR6.Get() == (HSEM_RLR6_LOCK | core)
case 7:
return HSEM.RLR7.Get() == (HSEM_RLR7_LOCK | core)
case 8:
return HSEM.RLR8.Get() == (HSEM_RLR8_LOCK | core)
case 9:
return HSEM.RLR9.Get() == (HSEM_RLR9_LOCK | core)
case 10:
return HSEM.RLR10.Get() == (HSEM_RLR10_LOCK | core)
case 11:
return HSEM.RLR11.Get() == (HSEM_RLR11_LOCK | core)
case 12:
return HSEM.RLR12.Get() == (HSEM_RLR12_LOCK | core)
case 13:
return HSEM.RLR13.Get() == (HSEM_RLR13_LOCK | core)
case 14:
return HSEM.RLR14.Get() == (HSEM_RLR14_LOCK | core)
case 15:
return HSEM.RLR15.Get() == (HSEM_RLR15_LOCK | core)
case 16:
return HSEM.RLR16.Get() == (HSEM_RLR16_LOCK | core)
case 17:
return HSEM.RLR17.Get() == (HSEM_RLR17_LOCK | core)
case 18:
return HSEM.RLR18.Get() == (HSEM_RLR18_LOCK | core)
case 19:
return HSEM.RLR19.Get() == (HSEM_RLR19_LOCK | core)
case 20:
return HSEM.RLR20.Get() == (HSEM_RLR20_LOCK | core)
case 21:
return HSEM.RLR21.Get() == (HSEM_RLR21_LOCK | core)
case 22:
return HSEM.RLR22.Get() == (HSEM_RLR22_LOCK | core)
case 23:
return HSEM.RLR23.Get() == (HSEM_RLR23_LOCK | core)
case 24:
return HSEM.RLR24.Get() == (HSEM_RLR24_LOCK | core)
case 25:
return HSEM.RLR25.Get() == (HSEM_RLR25_LOCK | core)
case 26:
return HSEM.RLR26.Get() == (HSEM_RLR26_LOCK | core)
case 27:
return HSEM.RLR27.Get() == (HSEM_RLR27_LOCK | core)
case 28:
return HSEM.RLR28.Get() == (HSEM_RLR28_LOCK | core)
case 29:
return HSEM.RLR29.Get() == (HSEM_RLR29_LOCK | core)
case 30:
return HSEM.RLR30.Get() == (HSEM_RLR30_LOCK | core)
case 31:
return HSEM.RLR31.Get() == (HSEM_RLR31_LOCK | core)
}
return false
}

// Unlock releases the lock on the receiver semaphore ID.
// Semaphores can be used to ensure synchronization between processes running on
// different cores. Unlock provides a non-blocking mechanism to unlock
// semaphores in an atomic way.
func (id HSEM_ID_Type) Unlock(core uint32) {
switch id {
case 0:
HSEM.R0.Set(core)
case 1:
HSEM.R1.Set(core)
case 2:
HSEM.R2.Set(core)
case 3:
HSEM.R3.Set(core)
case 4:
HSEM.R4.Set(core)
case 5:
HSEM.R5.Set(core)
case 6:
HSEM.R6.Set(core)
case 7:
HSEM.R7.Set(core)
case 8:
HSEM.R8.Set(core)
case 9:
HSEM.R9.Set(core)
case 10:
HSEM.R10.Set(core)
case 11:
HSEM.R11.Set(core)
case 12:
HSEM.R12.Set(core)
case 13:
HSEM.R13.Set(core)
case 14:
HSEM.R14.Set(core)
case 15:
HSEM.R15.Set(core)
case 16:
HSEM.R16.Set(core)
case 17:
HSEM.R17.Set(core)
case 18:
HSEM.R18.Set(core)
case 19:
HSEM.R19.Set(core)
case 20:
HSEM.R20.Set(core)
case 21:
HSEM.R21.Set(core)
case 22:
HSEM.R22.Set(core)
case 23:
HSEM.R23.Set(core)
case 24:
HSEM.R24.Set(core)
case 25:
HSEM.R25.Set(core)
case 26:
HSEM.R26.Set(core)
case 27:
HSEM.R27.Set(core)
case 28:
HSEM.R28.Set(core)
case 29:
HSEM.R29.Set(core)
case 30:
HSEM.R30.Set(core)
case 31:
HSEM.R31.Set(core)
}
}
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