Dieses Repository enthält die Implementierung eines RISC Prozessors mit VHDL, welche im Rahmen eines Projekts an der Universität Hamburg entstanden ist.
-
Updated
Jan 24, 2023 - VHDL
Dieses Repository enthält die Implementierung eines RISC Prozessors mit VHDL, welche im Rahmen eines Projekts an der Universität Hamburg entstanden ist.
Implementation of a simple 5-stage 32-bit pipelined processor and its assembler using VHDL and Python
EDRICO (Educational DHBW RISC-V Core) is a small 32-bit RISC-V core implementing the Integer base architecture and Zicsr extension. It was developed as part of a students project at the DHBW Ravensburg by Noah Wölki and Levi Bohnacker. Future developments (outside of the scope of DHBW Ravensburg) are planned to add further ISA extensions and imp…
Microprocessor without Interlocked Pipelined Stages (MIPS) architectures
Add a description, image, and links to the 32-bit topic page so that developers can more easily learn about it.
To associate your repository with the 32-bit topic, visit your repo's landing page and select "manage topics."