Over-engineered SDR development board
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Updated
May 28, 2024 - VHDL
Over-engineered SDR development board
A simple and scaleable Self Organizing Map implementation written in VHDL. Tested on ARTYA7-35T board.
A series of projects using the floating point division IP from Xilinx to perform floating point (single precision) division. Boards used: ZYBO and NEXYS4DDR (ARTIX-7)
Created project using a PCIe root-complex and endpoint on a Xilinx Artix-7.
Realtime Audio Processing on Artix-7 FPGA written in VHDL
An Artix 7 based dual channel oscilloscope.
Project to show in a BCD display a value set in binary
A collection of code from CDA 4240C: Design of Digital System and Lab
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