Reusable AXI Universal Verification Component built with SystemVerilog and UVM. Integrates into any testbench to accelerate design verification with modular agents, monitors, drivers, coverage, and scoreboard.
systemverilog axi uvm-verification axi-uvc axi-verification-using-uvm axi-protocol axi-protocol-verification-using-uvm axi-uvm-project
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Updated
Sep 24, 2025 - SystemVerilog