RTL data structure
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Apr 23, 2026 - SystemVerilog
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uvm-verification
Here are 128 public repositories matching this topic...
Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.
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Aug 9, 2020 - SystemVerilog
Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
simulation verification vip systemverilog questasim uvm verification-methodologies testbench semiconductor digital-design uvm-verification ahb2apb
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Mar 3, 2024 - SystemVerilog
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Feb 10, 2024 - SystemVerilog
Systemverilog and UVM exercises inspired by ziglings
asic verification systemverilog uvm systemverilog-simulation asic-verification uvm-verification systemverilog-test-bench systemverilog-constraint uvm-testbench
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Aug 23, 2026 - SystemVerilog
Configurable AXI4 Verification IP developed using UVM, featuring reusable master and slave agents, protocol checking, functional coverage, and scoreboard-based verification.
protocol randomization vip scoreboard systemverilog questasim uvm axi amba sva axi4 functional-coverage uvm-verification constrained-randomization asserti
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Mar 7, 2026 - SystemVerilog
Synthesizable AXI4 crossbar with a full UVM verification environment — RTL, SVA, coverage, stress, and CI.
ci verification rtl vcs systemverilog uvm qos arbitration backpressure sva crossbar questa axi4 jerkins uvm-verification hardware-validation
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Aug 21, 2025 - SystemVerilog
Getting started with SystemVerilog: Hardware Description Language for design and verification.
testing design asic fpga hardware verification rtl systemverilog hardware-designs hdl modelsim questasim uvm testbench systemverilog-hdl rtl-design uvm-verification
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Nov 5, 2025 - SystemVerilog
BDD Gherkin implementation in native SystemVerilog, based on UVM.
asic fpga bdd bdd-specs rtl verilog systemverilog uvm verilog-hdl bdd-framework asic-verification design-verification asic-design rtl-design soc-design soc-verification uvm-verification
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Nov 16, 2024 - SystemVerilog
RISC-V processor co-simulation using SystemVerilog HDL and UVM.
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Jun 15, 2024 - SystemVerilog
This repository is meant for learning UVM using SystemVerilog. Through a verification environment, some hardware verification concepts are applied for a calculator with the four basic operations.
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May 14, 2026 - SystemVerilog
Multi-Channel DDR Memory Controller Design with BFM-Based Verification and UVM-Style Testbench
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Aug 15, 2026 - Verilog
Sapphire SoC: RV32I RISC-V core optimized for FPGAs, featuring UVM verification, AXI4-Lite bus, FreeRTOS support, and Shakti-inspired design. Open-source under MIT license for embedded/IoT applications.
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Jun 27, 2025 - Verilog
A UVM-based verification environment for a multi-core, write-back L2 cache on 32-bit RISC-V, enforcing MESI coherence with L1 caches and interfacing to DRAM over AXI4-Lite.
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Jul 13, 2026 - SystemVerilog
Router 1 x3 is a Basic level Design of Wireless Fidelity Router Model • The top level consists of 4 blocks-3 FIFO{First In First Out Register) , 1 Register, 1 Synchroniser and 1 Control Block (FSM-Finite State Machine) • RTL and Testbench are coded in verilog and the waveforms are generated using Modelsim software. • The Synthesis was performed u
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May 13, 2024 - SystemVerilog
A synthesizable Gigabit Ethernet MAC IP core with full UVM verification environment.
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Jul 17, 2026 - SystemVerilog
An FPGA implementation of Cummings' Asynchronous FIFO
fpga rtl verilog xilinx synthesis systemverilog fifo uvm xilinx-fpga xilinx-vivado digilent hardware-description-language nexys4ddr universal-verification-methodology fpga-programming digilent-nexys-4-board synthesizable asynchronous-fifo uvm-verification register-transistor-level
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Apr 14, 2022 - SystemVerilog
A parameterizable Systolic Array Hardware Accelerator for CNNs implemented in SystemVerilog, optimized for high-throughput Matrix-Matrix Multiplications (GEMM) with an RTL-to-GDSII flow.
asic deep-learning cnn vivado systemverilog vlsi systolic-arrays rtl-design hardware-accelerator uvm-verification openlane skywater-sky130
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May 14, 2026 - Verilog
Verification of Advanced Encryption Standard (AES-128) Using the Universal Verification Methodology (UVM).
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Jan 28, 2025 - Verilog
This project uses UVM to verify an SPI Slave connected to internal RAM. It includes multiple agents (active and passive) and integrates assertion-based verification for both SPI and RAM behavior.
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May 5, 2025 - SystemVerilog
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