Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter using fractional floating point division.
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Updated
Aug 11, 2022 - Verilog
Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter using fractional floating point division.
This project implements a bit error rate tester. A PRBS (pseudo random bit sequence) is generated that can feed the DUT. The receiver compares the internally delayed transmitted signals with received signal and counts up an error counter if their logic levels differ.
Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device
Clock and UART Baud rate generation, radix-4 multiplier, function generator & accelerator wrappers.
Clock and UART Baud rate generation, radix-4 multiplier, function generator & accelerator wrappers.
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