🖥️ An assembler and hardware simulator for the Mano Basic Computer, a 16 bit computer.

The Mythical CPU Simulator for Real Students

Mini Von Neumann Processor Simulation with Java

Mips Virtual Machine is a software design to run MIPS microprocessor assembly code using JAVA Programming Language (JAVA SE). Developed by @feteiha , @khaledelhadary , @Hatemmamdoh , @Ehab-Fawzy

This project is a Computer Architecture Design and Data Path Simulator which simulates a modified MIPS datapath with pipelining written in Java.

⚛️ 👨‍💻 💥 A project based in Quantum Computing and Quantum Information Science. This project was built using Java and JUnit. The QuISL (Quantum Information Science Library) is a Java Library (or Toolbox/Framework), which will act as Simulator of this new technology, as also, will allow to build and study Quantum Circuits, Quantum Algorithms, amon…

Projekty na Arch3

Tomasulo algorithm's simulator

All working nand2tetris course projects

Computer Architecture and Machine Language class at MiraCosta. This course introduces the fundamental physical and structural concepts of assembly language programming. Topics include machine architecture, memory addressing, input/output, interrupts, control structures, compiling, and linking. Course material was supplied by nand2tetris.org

SEGA Dreamcast GDI parsing tool for GHIDRA

Java Implementation of an Advanced Processor Simulator

A Java implementation of the Little Man's Computer (LMC) with interactive features

Tournament Branch Predictor (Hybrid Predictor)

All codes Done during my Practical Session with Some Amazing Concepts

Some samples of my CS work from the 2019-2020 school year

imitated MIPS assembly arithmetic operations

The given project is an implementation of the three kinds of cache mapping systems- Direct, Associative and set Associative Mapping. The code has been provided in Java

CPU scoreboard for dynamically scheduling a pipeline which keeps track of every instruction in the instruction pipeline for maximum processor utilization

Inter-cache communication protocol (MOESI) for cache coherency in a multi-processor multi-core system.