Generate ATPG for fault detection on Verilog circuits. C++/QT
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Updated
Jul 7, 2022 - Verilog
Generate ATPG for fault detection on Verilog circuits. C++/QT
Verilog Codes for various digital circuits for labs at IIT Ropar, basic gates, adders & subtractors (half & full), ripple adders, multipliers and code converters.
A high-performance and versatile carry-lookahead (CLA) full adder designed for rapid addition of arbitrary x^y bit inputs.
Digital Electronics Course Projects
A collection of digital circuits using Verilog.
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