Image Processing Toolbox in Verilog using Basys3 FPGA
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Updated
Sep 19, 2023 - VHDL
Image Processing Toolbox in Verilog using Basys3 FPGA
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
Academic project for the course of Digital Systems Design. The aim of the project was to design and implement an IIR audio filter on FPGA
DSSS Wireless transmit-receive system in VHDL
Neander++ (Neander extended) implementation and testing in VHDL for Digital Systems' 2nd assignment.
A collection of useful material and personal projects from the Computer and Informatics Engineering Bachelor's degree program at the University of Aveiro.
Coffee vending machine implementation designed for FPGAs (DE2-115 kit)
Program the FPGA with mastermind game
INE5406 - Digital Systems
Design a digital circuit that encodes and decodes strings with CRC-8 algorithm with an optimal delay and number of components
Computer Architecture Project using VHDL
Project done for the course of "Specification and simulation of digital systems" at Politecnico di Torino, academic year 2015/2016.
Washing machine program using VHDL
Repositório com os projetos elaborados durante a disciplina de Sistemas Digitais I (PCS3115)
O objetivo do deste projeto foi modelar, programar e testar uma Unidade Lógica e Aritmética, de quatro operações, usando os conhecimentos adquiridos em Circuitos Lógicos e aplicados nas aulas práticas no laboratório de Sistemas Digitais.
VHDL Design for seven segment Displays number from 1-100
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