Here are
53 public repositories
matching this topic...
RISC-V 1 and 5-stage CPUs Described in Chisel for Implementation in an Altera FPGA
Updated
Oct 15, 2017
Scala
Frequency counter using a GPS receiver PPS output as its reference
Updated
Jul 21, 2018
Scala
IAMROOT RISCV Research Group
Updated
Dec 8, 2018
Scala
Chisel3 AXI4-{Lite, Full, Stream} Definitions
Updated
Dec 31, 2018
Scala
Collection of utilities to simplify FPGA accelerator design
Updated
Apr 12, 2019
Scala
A group of function-based and/or callback-styled abstraction for Chisel3.
Updated
Apr 23, 2019
Scala
Support Repository of "How to make RISC-V Microcomputer using FPGA for programmer"
Updated
Jul 30, 2019
Scala
『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ
Updated
Jul 30, 2019
Scala
A group of typed definition of AXI4 in Chisel3.
Updated
Aug 8, 2019
Scala
shdl6800: A 6800 processor written in SpinalHDL
Updated
Jan 12, 2020
Scala
A template Chisel project for the DE1SOC FPGA board
Updated
Feb 13, 2020
Scala
FPGA friendly Multiport memories (N-read-M-write) based on LVT
Updated
May 23, 2024
Scala
Updated
May 22, 2020
Scala
A Z80 CPU implemented in Chisel.
Updated
Sep 20, 2020
Scala
A lightweight Ethernet MAC Controller IP for FPGA prototyping
Updated
Oct 19, 2020
Scala
The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
Updated
Apr 11, 2021
Scala
A Scalable BFS Accelerator on FPGA-HBM Platform
Updated
Jul 30, 2021
Scala
Updated
Aug 1, 2021
Scala
A simple Chisel test project for myself to learn Chisel and FPGA.
Updated
Nov 8, 2021
Scala
CNN accelerator implemented with Spinal HDL
Updated
Dec 27, 2021
Scala
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