XLS: Accelerated HW Synthesis
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Updated
Jun 4, 2024 - C++
XLS: Accelerated HW Synthesis
FPGA Accelerator for CNN using Vivado HLS
A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
PandA-bambu public repository
Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
CHARM: Composing Heterogeneous Accelerators on Versal ACAP Architecture
Tutorials on HLS Design
HeteroCL-MLIR dialect for accelerator design
High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
HLS code for Network on Chip (NoC)
Monte Carlo Methods applied to the Black-Scholes financial market model
HLS for Networks-on-Chip
Implementation of time and space-tiled stencil in Vivado HLS.
FPGA acceleration of arbitrary precision floating point computations.
DaCH: dataflow cache for high-level synthesis.
Near-storage compute aware file system and FPGA operator pipelines.
Implementation of the N^2-formulation of N-body simulation with Vivado HLS for SDAccel platforms.
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