Academic project for the course of Digital Systems Design. The aim of the project was to design and implement an IIR audio filter on FPGA
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Updated
Mar 29, 2018 - VHDL
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iir-filters
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IIR audio filter in Verilog, running on Zedboard. Fractional integer coefficients.
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Updated
Feb 6, 2018 - VHDL
Multi-level second-order (Silva Steensgaard Structure) delta-sigma modulator
fpga
interpolation
matlab
vhdl
simulink
fixed-point
digital-signal-processing
overclock
fir-filter
oversampling
up-conversion
iir-filters
spartan6
sigma-delta-modulation
halfband-filter
noise-shaping-converter
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Updated
Jan 21, 2018 - VHDL
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