The Logic Gates generator is a command line program that makes use of Python to generate logic gate schematics of (theoretically) any size, along with their Karnaugh map.

convert the true table to logic equation, if possible, then minimize the equation.

Maps user input for a size three map; gives the numbering for size three, four and five maps.

Calculates Multiple Karnaugh Maps at once using Selenium and custom built parser. The program then converts the Boolean Expressions into Dataflow Verilog (VHDL)

A web-based graphical simple Karnaugh map solver, made with Unity.

Karnaugh-map for 2 , 3 and 4 variables in both sum of product and product of sum expressions, which takes min-terms or max-terms as input and return simplified expression with desired variables.