Carry Cut-Back Adder (CCBA) - An approximate adder circuit with artificially-built false timing paths
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Updated
Mar 28, 2020 - VHDL
Carry Cut-Back Adder (CCBA) - An approximate adder circuit with artificially-built false timing paths
Fully pipelined SHA2-256 VHDL description with circular buffers instead of shift registers for low power.
Laboratory sessions from the "Sistemi Elettronici a Basso Consumo" course (Low-Power Electronic Systems), part of the Master's degree in Embedded Systems (Electronic Engineering) at Politecnico di Torino, academic year 2019/2020.
The project begins with describing a digital circuit using VHDL and Xilinx Vivado 2018.3. It then optimizes the circuit using low-power techniques. Various strategies such as registering, clock gating, and a hybrid approach are tested to find the best solution.
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