3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.

FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.

A Xilinx Vivado project to implement a Microblaze SOC on FPGA to run C applications

Me playing with FPGAs & the Linux kernel

A series of projects using the floating point division IP from Xilinx to perform floating point (single precision) division. Boards used: ZYBO and NEXYS4DDR (ARTIX-7)

Arquitectura de Computadoras 2018-2019

hello world on microblaze

University Project (Class: Reconfigurable Computing)

VHDL implementation of SHA-256. Reconfigurable Computing course

Fibonacci implementation for FPGA (in VHDL) and for Microblaze processor for FPGA (in C)

International Data Encryption Algorithm implementation for FPGA (in VHDL) and Microblaze processor for FPGA (in C)

Personal FPGA Proyects mostly Xilinx / Vivado and Some Multisim

ASIC for executing vectorized gradient descent on linear regression problems.

Game of Balance is an accelerometer based maze navigation game, with added features of score and life, that is built on Nexys 4 DDR development board.

FPGA based Embedded Systems module assignment