Compiler for WLP4 (subset of C) and Assembler for MIPS Assembly
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Updated
Apr 28, 2024 - C++
Compiler for WLP4 (subset of C) and Assembler for MIPS Assembly
This repository is a curated collection of assignments, lab tasks, lab reports and projects that I've compiled during my journey through the Bachelor of Science program in Computer System Engineering.
Projeto de calculadora em Assembly feito em 2018 para a disciplina Arquitetura de Computadores.
This project implements a MIPS processor simulator in C++. It interprets a limited set of MIPS assembly, enabling the implementation of a functional processor. The system features an automated assembly-machine code translator and offers modes for testing and execution. Specialized modules handle operations like arithmetic, multiplexing, etc.
Examples of different coding in MIPS
The main purpose of this project is to understand MIPS Assembly language. The input of this program is a file consisting sequence of MIPS instructions in binary. Software simulates behaviour of MIPS CPU by reading instructions and changing values of registers. At the end program prints out the current value of the registers, which matcheswith th…
The main purpose of this project is to understand MIPS Assembly language. The input of this program is a file consisting sequence of MIPS instructions in binary. This version expands the first to implement behaviour of cache. At the end of the execution, the simulator reports the number of total cache hits and misses. These programs contain 500+…
Program that translates MAVN(Higher level MIPS assembler) assembly language to MIPS 32bit assembly language. It creates zero-byte files.
Intrinsics are high level functions implemented in C language and are based in some ISAs. The mainly purpose is simulate these architectures in SiNUCA (Simulator of Non-Uniforme Caches)..
assembler written for a subset of the MIPS instruction set
Assignments of the course COL216 - Computer Architecture taught in Second Sem, 2020-21 at IIT Delhi.
Design of a simulator of a multi-core processor and DRAM for a subset of MIPS instruction set architecture in C++. Course Project of COL216: Computer Architecture taught in Second Sem, 2020-21 at IIT Delhi
Mahl (MIPS assembly high level) is a simple compiler that adds a higher level of abstraction to regular MIPS assembly
This repository contains code for our project for the course CS335 - Compiler Design at IIT Kanpur.
COL216, Spring 2021. Building MIPS interpreter step-by-step over assignments. The last assignment is the completed interpreter. Details in reports attached.
A Multi-core MIPS ISA, with MRM and DRAM, Simulator. Prints what is happening in every clock cycle and the final content of registers and DRAM.
A compiler for a simple C-like programming language
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