Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022
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Updated
Sep 21, 2022 - VHDL
Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022
Custom CPU and GPU architectures to run GUI applications on an FPGA.
NSCSCC2022龙芯杯个人赛,MIPS32,59MHz经典五级流水线架构,易于初学者阅读(计算机组成原理,自己动手写CPU)
MIPS processor that performs matrix multiplication 3x3 based on VHDL and implemented in XILINX
The project implements a MIPS processor in VHDL, containing the code and test programs. It is a useful resource for learning about microprocessor design and the MIPS architecture, providing a practical demonstration and documentation for beginners and experienced designers.
Implementação da arquitetura MIPS Monociclo e Multiciclo para o FPGA Cyclone IV Altera utilizando VHDL.
Course project for Computer Design and Practice at HIT.
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