AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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Jul 25, 2024 - SystemVerilog
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network-on-chip
Here are 6 public repositories matching this topic...
Network on Chip Implementation written in SytemVerilog
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Aug 27, 2022 - SystemVerilog
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
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Jun 26, 2023 - SystemVerilog
RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
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Mar 19, 2018 - SystemVerilog
RTL design and implementation of a 4x4 Network-on-Chip (NoC) with a mesh topology. This project includes SystemVerilog modules for buffer units, routing units, switch allocators, switches, routers, and nodes, along with comprehensive high-level testing scenarios. Developed as part of a Core-Based Embedded System Design course.
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Jul 12, 2024 - SystemVerilog
System-Verilog implementation of the ACDMA crossbar
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Nov 25, 2018 - SystemVerilog
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