A nextpnr arch definition for the TuringTumble board game.
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Updated
Nov 5, 2022 - Verilog
A nextpnr arch definition for the TuringTumble board game.
Basic counter example in verilog for Tang Nano 20k using Yosys, Nextpnr and openFPGALoader.
Z80 + USB + TinyFPGA-BX in Verilog using open-source Yosys+NextPNR
Peripheral library 📚 for open source FPGAs based on iCE40. (Configured for ICESugar-Nano)
A blinky project for the ULX3S v3.0.3 FPGA board
Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.
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