openlane
Here are 12 public repositories matching this topic...
Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
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Mar 26, 2022 - Verilog
CLEAR is an Open Source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC design tools used to create it.
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Mar 19, 2022 - Verilog
This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-source EDA tool which gives RTL to GDSII flow.
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Jul 19, 2022 - Verilog
This is part of EC383 - Mini Project in VLSI Design.
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May 8, 2022 - Verilog
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
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Jan 23, 2024 - Verilog
This repository offers a compact design verification flow using OpenLANE. Scripts cover synthesis correctness, functional and power verification, DRC/LVS, timing analysis, and reliability checks. Contributions are welcome.
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Mar 8, 2024 - Verilog
Picorv32-IM with exact and approximate SIMD multiplication extensions. The SIMD modules can be accessed with custom RISC-V Instruction to perform dual/quad 8-bit multiplications.
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Jan 28, 2024 - Verilog
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