8-bit MISC processor with pipelining
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Updated
Dec 13, 2021 - VHDL
8-bit MISC processor with pipelining
A pipelined implementation of a MIPS processor that was optimized to use data forwarding, caching and branch prediction.
Implementation of a simplified synthesisable RISC-Processor with a 4 stage pipelining architecture written in VHDL.
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