risc-v
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
Here are 141 public repositories matching this topic...
Various programs written in Assembly for RISC-V CPUs
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Apr 25, 2021 - Assembly
A collection of RISC-V assembly programs I wrote for use with RARS
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Jun 2, 2023 - Assembly
RISC-V: RV64G Linux assembly and payloads from the ground up
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Jun 28, 2019 - Assembly
Repositório com intuito de reunir lista com as instruções mais básicas para risc-v para inteiros 32 bits e alguns exemplos úteis.
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Apr 24, 2021 - Assembly
Collection of RISC-V assembly projects from my UC Davis Computer Architecture class. Each project features unique objectives focused on various aspects of assembly programming such as calculating mathematical equations, sorting arrays, and implementing search algorithms. All programs are designed to work in the RARS simulator.
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Mar 22, 2021 - Assembly
A bare metal system for the 32-bit RISC-V processor using the Longan Nano development board (GD32VF103).
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Sep 23, 2023 - Assembly