risc-v
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
Here are 142 public repositories matching this topic...
RISC-V: RV64G Linux assembly and payloads from the ground up
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Jun 28, 2019 - Assembly
[HIGHLY WIP] RustISC-V: (userland) RISC-V(32) emulator written in Rust
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Nov 4, 2019 - Assembly
Implementation of common functions using RISC-V assembly.
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Dec 11, 2019 - Assembly
RISC-V programs with MARS system calls
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Mar 18, 2020 - Assembly
An instruction set simulator (ISS) for the RV32/64I subset of the RISC-V instruction set.
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Nov 5, 2020 - Assembly
This Compiler can translate MiniJava into K210 RISC-V assembly.
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Jan 7, 2021 - Assembly
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Jan 10, 2021 - Assembly