risc-v
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
Here are 108 public repositories matching this topic...
A small example for running Rust code on RISC-V
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Mar 1, 2020 - Rust
Examples of embedded application in minimalistic style for RISC-V in Rust
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Mar 16, 2020 - Rust
Mirror; Work-in-progress software-rendering Vulkan implementation
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Apr 1, 2020 - Rust
Sample Rust programs for the GD32VF103
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Sep 6, 2020 - Rust
Rust implementation of spike's RISC-V disassembler, spike-dasm
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Dec 1, 2020 - Rust
A multi-task multi-core operational system written in Rust for the Risc-V processor family.
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Dec 6, 2020 - Rust
Trying embedded Rust on the Pinecil GD32VF103 RISC-V device.
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Feb 21, 2021 - Rust
RiscV Fun Machine (virtual console)
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Apr 6, 2021 - Rust
[EXPERIMENTAL] RISC-V platform crate for Drone, an Embedded Operating System.
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Apr 9, 2021 - Rust
A 5-stage pipelining RISC-V 32I simulator written in Rust.
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Apr 21, 2021 - Rust