Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit
-
Updated
Apr 19, 2024 - Verilog
Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit
Systolic-array based Deep Learning Accelerator generator
This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times faster than a software running the same algorithm.
Template for project1 TPU
EE599 Accelerated Computing on FPGA
This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.
Add a description, image, and links to the systolic-arrays topic page so that developers can more easily learn about it.
To associate your repository with the systolic-arrays topic, visit your repo's landing page and select "manage topics."