A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
-
Updated
Dec 2, 2019 - Verilog
A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
Add a description, image, and links to the tape-out topic page so that developers can more easily learn about it.
To associate your repository with the tape-out topic, visit your repo's landing page and select "manage topics."