SystemVerilog RTL and UVM RAL model generators for RgGen
-
Updated
Jun 7, 2024 - Ruby
SystemVerilog RTL and UVM RAL model generators for RgGen
This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
Code generation tool for control and status registers
Add a description, image, and links to the uvm topic page so that developers can more easily learn about it.
To associate your repository with the uvm topic, visit your repo's landing page and select "manage topics."