A complete classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.
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Updated
Sep 3, 2019 - Verilog
A complete classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.
Self playing Flappy Bird game with machine learning on FPGA with genetic algoritm .
Hardware Description Language(HDL) based codes using Verilog & VHDL for reference.
This repo contains educational projects, connected with FPGA. All program are written for Altera Quartus IV.
A dump for my VHDL projects, because I want to have a better understanding of Verilog and also Logic circuits.
Bilgisayar Organizasyonu Verilog Projeleri
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