A dump for my VHDL projects, because I want to have a better understanding of Verilog and also Logic circuits.
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Updated
May 24, 2024 - Verilog
A dump for my VHDL projects, because I want to have a better understanding of Verilog and also Logic circuits.
This repo contains educational projects, connected with FPGA. All program are written for Altera Quartus IV.
Hardware Description Language(HDL) based codes using Verilog & VHDL for reference.
A complete classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.
Self playing Flappy Bird game with machine learning on FPGA with genetic algoritm .
Bilgisayar Organizasyonu Verilog Projeleri
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