Verilog programs in gate level, dataflow & behavioural modelling with testbenches written in intel FPGA tested with ModelSim simulator
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Feb 21, 2024 - Verilog
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vlsi-design
Here are 35 public repositories matching this topic...
Codes performed in labs using Xilinx ISE 14.7
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Sep 15, 2020 - Verilog
The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requiring robust and reliable memory handling.
memory
verilog
sram
memory-management
vivado
questasim
sdram
sdram-controller
memory-controller
verilog-project
vlsi-design
sram-controller
sram-controller-advanced
sram-features-power-security-brust
verlog-hdl
enhanched-sram-controller
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Oct 21, 2024 - Verilog
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Aug 20, 2022 - Verilog
This is part of EC383 - Mini Project in VLSI Design.
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May 8, 2022 - Verilog
Universal Shift Register is a register which can be configured to load and/or retrieve the data in any mode (either serial or parallel) by shifting it either towards right or towards left. In other words, a combined design of unidirectional (either right- or left-shift of data bits as in case of SISO, SIPO, PISO, PIPO) and bidirectional shift re…
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Jul 25, 2021 - Verilog
A full adder circuit is central to most digital circuits that perform addition or subtraction. It is so called because it adds together two binary digits, plus a carry-in digit to produce a sum and carry-out digit.1 It therefore has three inputs and two outputs.
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Jul 25, 2021 - Verilog
This repository contains code files for VLSI Laboratory - EC39004, conducted in Spring 2024 at IIT Kharagpur
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Mar 10, 2024 - Verilog
This is the design of a work-conserving Round Robin Arbiter, with four (4) request queues. This was implemented on an FPGA(DE10-Lite).
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Aug 11, 2022 - Verilog
This repository holds some different architectures for multipliers which have been used alongwith verilog code and testbench as well.
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Jun 8, 2023 - Verilog
Introducing an innovative H.264 decoder project with QCIF resolution, designed to enhance video playback performance. This open-source GitHub repository offers a robust solution for decoding H.264 video streams, enabling seamless playback on various platforms.
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Oct 27, 2023 - Verilog
THIS REPOSITORY CONTAINS DESIGN FILES FOR SPI TO 32 DIGITAL IO EXPANSION MODULE
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Nov 6, 2021 - Verilog
A compilation of various projects programmed fully in Verilog.
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Apr 20, 2023 - Verilog
This project proposes to demonstrate the capabilities and scope of Verilog HDL by implementing the control system of an automatic washing machine. The above mentioned objective by implementing the Control System of an automatic washing using the Finite State Machine model. The washing machine control system generates all the control signals requ…
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Sep 6, 2021 - Verilog
ALU (Arithmetic and Logic Unit), Ripple carry adder, Half adder and full adder are designed using all 3 styles (structural, behavioral, dataflow) and tested by generating stimulus using testbench
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Mar 27, 2023 - Verilog
Created AMD-Am2901 chip clone (4-bit ALU) with Cadence Virtuoso from a transistor level, manually creating datapath and generating control via CAD. Skills employed: Cadence Virtuoso, Logic (VLSI) Design, Verilog
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Jul 2, 2023 - Verilog
Design of real time clock(RTC) using Verilog HDL
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Dec 5, 2021 - Verilog
This repository contains Verilog HDL implementations of Half Adders, Full Adders, and 4-bit Adders, designed at three different abstraction levels: Gate Level, Dataflow Level, and Behavioral Level. These designs are fundamental to digital electronics, and this project showcases the versatility of Verilog in modeling and simulating digital circuits.
circuit-simulation
verilog-hdl
test-bench
half-adder
hardware-description-language
digital-electronics
full-adder
verilog-project
vlsi-design
rtl-design
arithmetic-operations
fpga-verilog
logic-circuit-design
behavioral-modeling
4-bit-adder
verilog-adders
gate-level-design
dataflow-design
digital-circuit-simulation
hdl-coding
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Aug 24, 2024 - Verilog
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Aug 20, 2022 - Verilog
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