Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
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Updated
May 20, 2020 - Verilog
Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
This repo contains golden vector and randomization testbenches for SRAM module.
Codes performed in labs using Xilinx ISE 14.7
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