Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

Microshift Compression: An Efficient Image Compression Algorithm for Hardware

Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.

The Repository contains the code of various Digital Circuits

UART - RTL Design and Verification

VLSI Design - Spring 2022

This is part of EC383 - Mini Project in VLSI Design.

This project proposes to demonstrate the capabilities and scope of Verilog HDL by implementing the control system of an automatic washing machine. The above mentioned objective by implementing the Control System of an automatic washing using the Finite State Machine model. The washing machine control system generates all the control signals requ…

Universal Shift Register is a register which can be configured to load and/or retrieve the data in any mode (either serial or parallel) by shifting it either towards right or towards left. In other words, a combined design of unidirectional (either right- or left-shift of data bits as in case of SISO, SIPO, PISO, PIPO) and bidirectional shift re…

ALU (Arithmetic and Logic Unit), Ripple carry adder, Half adder and full adder are designed using all 3 styles (structural, behavioral, dataflow) and tested by generating stimulus using testbench

This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out

THIS REPOSITORY CONTAINS DESIGN FILES FOR SPI TO 32 DIGITAL IO EXPANSION MODULE

BRACU CSE460: VLSI Design Lab, Fall- 2021

TicTacToe game using verilog hdl and implementation in spartan-3 FPGA board

This repo contains golden vector and randomization testbenches for SRAM module.

Design of real time clock(RTC) using Verilog HDL

Codes performed in labs using Xilinx ISE 14.7

A full adder circuit is central to most digital circuits that perform addition or subtraction. It is so called because it adds together two binary digits, plus a carry-in digit to produce a sum and carry-out digit.1 It therefore has three inputs and two outputs.