Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
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Updated
Jun 6, 2024 - Verilog
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
This repository contains code files for VLSI Laboratory - EC39004, conducted in Spring 2024 at IIT Kharagpur
Verilog programs in gate level, dataflow & behavioural modelling with testbenches written in intel FPGA tested with ModelSim simulator
GitHub repository dedicated to VLSI ASIC Design using open-source tools! A simple Vedic Multiplier is Forged, through the entire RTL to GDS process that meets various PPA
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
Introducing an innovative H.264 decoder project with QCIF resolution, designed to enhance video playback performance. This open-source GitHub repository offers a robust solution for decoding H.264 video streams, enabling seamless playback on various platforms.
The Repository contains the code of various Digital Circuits
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
Created AMD-Am2901 chip clone (4-bit ALU) with Cadence Virtuoso from a transistor level, manually creating datapath and generating control via CAD. Skills employed: Cadence Virtuoso, Logic (VLSI) Design, Verilog
This repository holds some different architectures for multipliers which have been used alongwith verilog code and testbench as well.
A compilation of various projects programmed fully in Verilog.
ALU (Arithmetic and Logic Unit), Ripple carry adder, Half adder and full adder are designed using all 3 styles (structural, behavioral, dataflow) and tested by generating stimulus using testbench
This is the design of a work-conserving Round Robin Arbiter, with four (4) request queues. This was implemented on an FPGA(DE10-Lite).
Design of 32-bit MIPS Processor
This is part of EC383 - Mini Project in VLSI Design.
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