RTL to GDSII Physical Design using OpenLane and Opensource Softwares
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Updated
Oct 4, 2024 - Verilog
RTL to GDSII Physical Design using OpenLane and Opensource Softwares
Standard Cell Library based Memory Compiler using FF/Latch cells
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
5 Day TCL begginer to advanced training workshop by VSD
A High-performance Timing Analysis Tool for VLSI Systems
This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-source EDA tool which gives RTL to GDSII flow.
A Standalone Structural Verilog Parser
IEEE DATC Robust Design Flow 2021.
In electronics, a multiplexer (or mux; spelled sometimes as multiplexer, also known as a data selector, is a device that selects between several analog or digital input signals and forwards the selected input to a single output line.
This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSII Flow is implemented with Openlane using Skywater130nm PDK. Custom-designed standard cells with Sky130 PDK are also used in the flow. Timing Optimisa…
DATC RDF
Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
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