cdsAsync: An Asynchronous VLSI Toolset & Schematic Library
-
Updated
Aug 10, 2019 - Verilog
cdsAsync: An Asynchronous VLSI Toolset & Schematic Library
VLSI System Design Practice Lab
DATC RDF
All the projects and assignments done as part of VLSI course.
work done as part of VLSI Design practice course
Projects and labs from the courses dictated in https://www.coursera.org/specializations/fpga-design. Projects are sometimes simulated, and implemented in either a MAX10-Lite or an Arrow MAX1000 board.-
Computer Architecture -VLSI -Verilog Codes-Xilinx-Irsim
16-bit DADDA Multiplier design using using 5:2 compressor as the major reduction compressor and 4:2 compressor; and FullAdder and HalfAdder to simulate 3:2 and 2:2 compressors respectively.
Given A and B are 64-bit inputs. With two selection lines s1 and s0 to perform the operations, A+B, A-B, AB, C+AB using Baugh Wooley multiplier
SHA-2 (Secure Hash Algorithm 2), of which SHA-256 is a part, is one of the most popular hashing algorithms out there.
In electronics, a multiplexer (or mux; spelled sometimes as multiplexer, also known as a data selector, is a device that selects between several analog or digital input signals and forwards the selected input to a single output line.
A full adder circuit is central to most digital circuits that perform addition or subtraction. It is so called because it adds together two binary digits, plus a carry-in digit to produce a sum and carry-out digit.1 It therefore has three inputs and two outputs.
SPI is a synchronous, full duplex master-slave-based interface. The data from the master or the slave is synchronized on the rising or falling clock edge based on mode .Both master and slave can transmit data at the same time. The SPI interface got 4 wires.
Add a description, image, and links to the vlsi topic page so that developers can more easily learn about it.
To associate your repository with the vlsi topic, visit your repo's landing page and select "manage topics."