2 bit random number generation under data encryption using Synopsys Custom Compiler in 32nm CMOS Technology
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Updated
Feb 24, 2022
2 bit random number generation under data encryption using Synopsys Custom Compiler in 32nm CMOS Technology
A quantum approach to the problem of Visible Surface Determination (VSD) using the Q# SDK
This repo contains documentation of the "VSD Open Digital-Design-on-FPGA" tutorial.
Creating this repo to document the learnings from the workshop Advanced Physical Design using OpenLANE/SKY130 conducted by VSD
This repo contains documentation of the "VSD Open On-Chip Clock Multiplier (PLL) on OSU180" tutorial.
Report of the contents learned in the 5-day workshop by VSD regarding the open-source EDA tools in the VLSI industry
Python SDK to communicate with Aspose.Diagram REST API. Process Visio® files in the Cloud with zero initial cost.
This script builds openlane and all its dependencies on an Ubuntu (only) System.
This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop
This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an openlane flow.
Library/Tools to convert Microsoft (MS) Visio documents (VSS and VSD) to SVG
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