Implementation of a MIPS processor on a Xilinx Artix-7 FPGA.
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Updated
May 19, 2023 - Verilog
Implementation of a MIPS processor on a Xilinx Artix-7 FPGA.
Verilog UART implementation with Vivado build scripts to test loopback on Xilinx Arty board
Bare metal (without embedded OS) DC motor speed control system
南理工数字系统综合实验实验代码/实验报告
UART implementation using Verilog HDL
Cyber Melody 2 on MIPS!
SPI module for Nexys 4 Artix-7 FPGA Trainer Board
This is a functioning MIPS CPU designed in Verilog to run an an xilinx fpga.
A coocbook of HDL (primarily Verilog) modules
Quick Verilog Module Isolator - Isolates a design for testing.
University projects on FPGA including the implementation of a digital clock on a seven segment and a calculator getting inputs from a ps2 keyboard and showing the result on the seven segment
4 request first come first serve arbiter design using verilog HDL
Custom graphics driver using Verilog on Xilinx FPGA platform.
Lab projects using Verilog HDL
CECS 490A/490B Course; Senior Project Design
RISC based 8-bits five stage pipelined processor, operating at 585 MHz clock frequency with 19 I/O pins and 28 instructions having 5 Addressing formats. Tested on Xilinx Artix-7 FPGA.
Verilog code that could run on Nexys3 (Spartan-6)
FPGA Messbauer hardware (generator, emulation of signal from gamma-source registered and amplified
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