xilinx-ise

An 8-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics which is proved to consume less power and faster than conventional multipliers.

simulation synthesis verilog-hdl xilinx-ise multiplier adders vedic-mathematics

Updated Jul 27, 2020
Verilog

SamuelGong / SingleCycleCPU

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A single cycle CPU running MIPS instructions on Xilinx FPGA

cpu fpga xilinx-ise computer-organization single-cycle

Updated Aug 27, 2017
Verilog

PrayagS / MIPS_16bit

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16-bit MIPS processor implemented in Verilog (as a part of Computer Organisation course)

cpu mips verilog computer-architecture xilinx-ise

Updated Dec 30, 2019
Verilog

MossbauerLab / MessbauerTestEnvironment

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FPGA Messbauer hardware (generator, emulation of signal from gamma-source registered and amplified

science fpga emulation verilog ise spectrometry spectroscopy xilinx-fpga xilinx-ise spartan-programming mossbauer-effect spartan6 signal-generator fpga-signal-generator

Updated Aug 26, 2019
Verilog

SamuelGong / MultipleCycleCPU

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A multiple cycle CPU running MIPS instructions on Xilinx FPGA

cpu fpga xilinx-ise computer-organization multiple-cycle

Updated Aug 27, 2017
Verilog

MaharshSuryawala / Microprocessor-Without-Interlocked-Pipeline-Stages-MIPS

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RISC based 8-bits five stage pipelined processor, operating at 585 MHz clock frequency with 19 I/O pins and 28 instructions having 5 Addressing formats. Tested on Xilinx Artix-7 FPGA.

vhdl verilog microprocessor opcodes xilinx-fpga xilinx-ise register-bank

Updated Sep 3, 2020
Verilog

ujjawalece / AES-and-DES-Implementation-in-Verilog-Xilinx-

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cryptography encryption aes-128 verilog decryption xilinx-ise

Updated Jul 12, 2021
Verilog

SamuelGong / MicroprogrammingProcessor

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Microgramming technology applied to my multiple cycle CPU

cpu fpga microprogramming xilinx-ise computer-organization multiple-cycle

Updated Aug 27, 2017
Verilog

Venkaraddi7 / Elevator_Controller

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To implement the elevator controller, we used Verilog as HDL. The focus of our project was the implementation and verification of a controller for a basic elevator functionality. We also proposed a methodology that utilizes the SCAN algorithm to enhance the efficiency and reliability of the controller.

project verilog-hdl xilinx-ise isim elevator-controller rtl-coding

Updated May 14, 2023
Verilog

Jamesits / verilog-basic-blocks

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数电作业

verilog xilinx-ise verilog-components

Updated Jan 11, 2018
Verilog

teekamkhandelwal / Uart_tx_main

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Uart=Stands for Universal Asynchronous Reception and Transmission (UART).A simple serial communication protocol that allows the host communicates with the auxiliary device.UART supports bi-directional, asynchronous and serial data transmission.It has two data lines, one to transmit (TX) and another to receive (RX) which is used to communicate th…

fpga questasim verilog-hdl uart-protocol xilinx-ise verilog-project