FPGA Cryptography for High-Level Synthesis
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Updated
Aug 3, 2021 - C++
FPGA Cryptography for High-Level Synthesis
EXPERIMENTAL Verilog (and HLS, C++, Python, OpenCL) implementation of the RC4 stream cipher.
localization of sound source by cross-correlating three ΣΔ-modulated microphone signals in a zynq FPGA SoC
High Level synthesis of data transfer in Vivado, Vivado HLS
High level synthesis projects and practices
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