Bus bridges and other odds and ends
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Updated
Jan 12, 2024 - Verilog
Bus bridges and other odds and ends
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)
This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session
Extremely basic CortexM0 SoC based on ARM DesignStart Eval
Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
Repository to store all design and testbench files for Senior Design
透過數位邏輯結合VHDL與Verilog的過程,作為從基礎數位邏輯到計算機系統結構,並實作出一顆CPU的教學書籍,希望未來可以成為教學範例檔案。目前將開發轉移到GitLab,因為可以呈現數學與MUL圖。
Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.
A single cycle MIPS RISC-V CPU Core using Verilog
This project aims to design a hardware encryption and decryption scheme for the Data Encryption Standard (DES) algorithm
A finite state machine controlled calculator written using Verilog in Xilinx Vivado targeting the Nexys 4 DDR FPGA Board
100 Days challenge to improve digital desinging using languages like Verilog & SystemVerilog
FPGA based single player game
Suspicious Package Detection and Alert System for Public Spaces
This repository contains source code for labs and projects involving FPGA and Verilog based designs
Door Lock with provision to set the password in Real Time
A custom processor implemented in Verilog HDL for image down sampling for UOM's EN3030 Circuits and Systems Design module ❄
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