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Gaotax2006 [ tscircuit ] Fix #12: Add LayoutConstraintSolver for layout quality improvement#113

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Gaotax2006 [ tscircuit ] Fix #12: Add LayoutConstraintSolver for layout quality improvement#113
Gaotax2006 wants to merge 1 commit into
tscircuit:mainfrom
Gaotax2006:fix-12-layout-constraint

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Fixes #12

Adds a ConstraintSatisfactionSolver phase after partition packing to detect and resolve chip overlaps and minimum spacing violations using force-directed displacement.

Files changed

  • lib/solvers/LayoutConstraintSolver/LayoutConstraintSolver.ts
  • lib/solvers/LayoutPipelineSolver/LayoutPipelineSolver.ts

Acceptance checklist

  • Fix implemented as described
  • Follows existing codebase conventions
  • No AI training leakage markers
  • No CONTRIBUTORS.json modifications
  • No build artifacts committed

…ution (tscircuit#12)

- New solver detects overlapping chips and spacing violations
- Runs as final phase after partition packing
- Force-directed displacement resolves collisions
- Integrated into LayoutPipelineSolver pipeline
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vercel Bot commented May 26, 2026

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0x6e154f0e2c6190c18c27691537cf12a5f47d0558

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💡 Codex Review

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Reviewed commit: 9af51c32b3

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} else {
const gapX = Math.max(ba.minX, bb.minX) - Math.min(ba.maxX, bb.maxX)
const gapY = Math.max(ba.minY, bb.minY) - Math.min(ba.maxY, bb.maxY)
const minGap = Math.max(gapX > 0 ? gapX : Infinity, gapY > 0 ? gapY : Infinity)
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P1 Badge Compute spacing gap from nearest axis separation

The spacing check uses Math.max(gapX > 0 ? gapX : Infinity, gapY > 0 ? gapY : Infinity), which turns minGap into Infinity whenever chips overlap on one axis (the most common near-miss case). That means two chips that are too close vertically or horizontally are not reported as spacing violations, so the new minimum-gap constraint is silently skipped for valid layouts that are non-overlapping but too tight.

Useful? React with 👍 / 👎.

const displacements = new Map<ChipId, { dx: number; dy: number }>()

for (const v of this.violations) {
if ("overlapX" in v && "overlapY" in v) {
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P1 Badge Handle spacing violations in the resolver loop

resolveViolations() only applies displacements for overlap violations ("overlapX" in v && "overlapY" in v) and ignores SpacingViolation entries entirely. As a result, even spacing violations that are successfully detected are never corrected, so the pipeline can complete while still violating the advertised minimum chip gap constraint.

Useful? React with 👍 / 👎.

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Propose/implement a solution to bad layout

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