Newton-Raphson reciprocal unit to replace the VWAP divider

[tylrcc]

VWAP is num_acc / den_acc and the denominator is data-dependent, so it cannot be a shift. Today it is a synth-time divide in rtl/mac_engine.v. It works, it is slow, and it eats a pile of LUTs.

Goal: a small pipelined reciprocal (Newton-Raphson on den_acc, then multiply) in a new rtl/recip_unit.v, so the divide stops gating timing.

Notes

• Has to stay bit-accurate against sim/reference.py (floor of num // den). If a couple of LSBs differ, the model is the spec, match it or update both together.
• Watch the zero-volume window case: den == 0 currently falls back to SMA, keep that.
• A pipeline here pairs well with Register the multiplier and pipeline the accumulator update #1 (the latency budget).

Done when: the divider is gone, make sim passes, and it closes timing.