Switch PRCI to HarnessBinder/IOBinders #900
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Wow I forgot I made this PR. Can we get this looked at before I forget more about what happened here. @davidbiancolin @abejgonzalez |
| @@ -324,6 +325,21 @@ class WithSimDromajoBridge extends ComposeHarnessBinder({ | |||
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| class WithTieOffCustomBootPin extends OverrideHarnessBinder({ | |||
| (system: CanHavePeripheryCustomBootPin, th: HasHarnessSignalReferences, ports: Seq[Bool]) => { | |||
| ports.foreach(_ := false.B) | |||
| val pin = PlusArg("custom_boot_pin", width=1) | |||
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We should figure out how to get PlusArg to work with FireSim. Seems like a chill ugrad project.
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I'll add it to the CY meeting notes. Additionally, I think this harness binder name should probably change since it isn't strictly a tie-off anymore. Maybe something like WithCustomBootPinPlusArg?
generators/chipyard/src/main/scala/clocking/TileResetSetter.scala
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generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
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jerryz123
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| @@ -324,6 +325,21 @@ class WithSimDromajoBridge extends ComposeHarnessBinder({ | |||
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| class WithTieOffCustomBootPin extends OverrideHarnessBinder({ | |||
| (system: CanHavePeripheryCustomBootPin, th: HasHarnessSignalReferences, ports: Seq[Bool]) => { | |||
| ports.foreach(_ := false.B) | |||
| val pin = PlusArg("custom_boot_pin", width=1) | |||
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We should figure out how to get PlusArg to work with FireSim. Seems like a chill ugrad project.
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Two things you need to do:
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I believe these should be the correct frequencies for the |
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This should be ready for merge. (Reminder to self to merge-commit to avoid breaking recursive fsim-as-top) |
Type of change: new feature
Impact: rtl change
Release Notes
This change makes PRCI more "Chipyard-like". A system trait contains PRCI control registers to be able to independently control clock/reset to the tiles.
The PRCI graph is driven in the IOBinder, which contains different types of clock-driving patterns (FireSim vs RTL-sim vs FPGA-proto vs tapeout).
Harness binders can pass in any signals that the IOBinder clock driver might need, as usual.
The default ChipyardPRCI implementation contains reset-ctrl registers to allow MMIO to bring harts in and out of reset.
The default implementation also allows MMIO to selectively clock-gate harts (this feature is disabled in FireSim).