Chipyard Release 1.15.0

Chipyard 1.15.0 adds BOOM performance monitoring, new FPGA platforms, integer-only Saturn vector configurations, and updates to the RISC-V toolchain, simulation infrastructure, and documentation.

Major Features

• BOOM v3 performance monitoring with a new PMU library, per-tile event manifests, and optional memory-mapped counters.
• FireSim support and sample bitstreams for Corigine MimicTurbo GT and Xilinx Alveo V80.
• Preliminary Linux AArch64 support, with CIRCT compiled from source. Tested on ARM Neoverse N1 cores.
• GCC 16 + multi-lib enabled RISC-V toolchain support via ucb-bar riscv-tools v1.0.10 (https://anaconda.org/channels/ucb-bar/packages/riscv-tools/overview).
• Integer-only Saturn vector configurations and fixes for vector arithmetic, immediate decoding, and segmented stores.
• Genesys 2 and ZCU104 FPGA prototyping support, plus a SPEC CPU 2026 workload integration.
• Move to Starlight documentation, reorganized CI flow to run on GitHub runners, and nightly Chipyard Docker image builds.

Full Release Notes

Added

• Added the PMU generator library and SmallBoomV3PMUConfig, DualSmallBoomV3PMUConfig, and MediumBoomV3PMUConfig, with memory-mapped performance counters in each BOOM tile (by @iansseijelly in #2387).
• Added Corigine MimicTurbo GT and Xilinx Alveo V80 FireSim build recipes and prebuilt single-core Rocket bitstreams (by @raghav-g13 in #2385).
• Added With8GiBDRAM and FireSimMegaBoom8GiBDRAMConfig for FireSim targets with 8 GiB of target DRAM (by @Ferran-Hermida-Rivera in #2391).
• Added Linux AArch64 setup support and full/lean linux-aarch64 lockfiles; CIRCT builds from source on hosts without a matching prebuilt archive (by @jimfangx in #2381).
• Added Genesys 2 and ZCU104 FPGA configurations, documentation, and ZCU104 SD boot support (by Vladimir Milovanović @milovanovic and Nikola Petrovic @pznikola in #2372).
• Added the SPEC CPU 2026 workload submodule (by @angelacu1 in #2357).
• Added run-asm-tests-fast and run-bmark-tests-fast targets for running ISA tests and benchmarks without instruction logs, and a script for generating per-generator release logs (by @jimfangx in #2382).

Changed

• Updated riscv-tools from 1.0.6 to 1.0.10, moving the RISC-V toolchains to GCC 16 and separating scalar/vector Linux multilib installations. Updated the host GCC/G++ requirements to the GCC 15 series (by @jimfangx in #2380 and c3876234).
• Migrated the documentation frontend to Astro/Starlight while retaining the RST sources and Sphinx conversion step. Added live rebuilding, version selection, dark-mode improvements, and PDF generation support (by @jimfangx in #2361, #2362, and #2363).
• Reorganized CI into reusable setup, documentation, generator, FireSim, and container workflows, with configuration-driven generator tests and FireSim FPGA/metasimulation tests (by @jimfangx in #2382).
• Updated the FireChip tracing code for the libdwarf 2.1 API, replaced legacy ctags with universal-ctags, and pinned pydantic<2 for Hammer compatibility (by @jimfangx in #2380).
• Updated Rocket Chip, BOOM, Saturn, testchipip, the inclusive cache, FireSim, FireMarshal, FPGA Shells, Baremetal-IDE, CoreMark, libgloss, and the proxy kernel.

Fixed

• Passed the elaborated device map, custom CSRs, register widths, and PMP CSR count to Spike cosimulation, while excluding the Debug Module from the emulated device map (by @Ferran-Hermida-Rivera in #2368, with the testchipip bump in #2369).
• Fixed setup on hosts whose exact glibc version has no published Conda sysroot. Setup selects a published version no newer than the host, handles inline comments in the pin, and preserves the existing pin when it cannot select a suitable version (by @jimfangx, co-authored by @cwssemi, adapting #2374 in e184ee9b).
• Preserved existing lockfiles when a Conda solve fails by generating replacements at temporary paths and moving them into place only after successful solves (by @jimfangx, co-authored by @cwssemi, in e184ee9b).
• Built scalar RISC-V benchmarks with rv64gc and vector benchmarks with rv64gcv, so ordinary benchmarks do not require vector-capable cores (by @jimfangx in 371ab92d).
• Added an atexit workaround for the nano-Newlib exit path used by the bare-metal C tests. Added missing <stdio.h> includes and removed the extra full-libc link workaround for cpp-hello (by @jimfangx in 371ab92d and c3876234).
• Fixed compilation of VCS-generated C with newer host GCC versions by downgrading implicit-function-declaration errors in the VCS code-generation compiler (by @jimfangx in c3876234).
• Changed the SPEC CPU 2026 submodule URL to HTTPS and excluded it from default initialization, matching the SPEC CPU 2017 handling (by @Ferran-Hermida-Rivera in #2370).

Other Direct Commits / Release-Branch Updates

• Updated the FireMarshal and CoreMark pins, including restoration of the standard lp64d Buildroot and BusyBox settings with the corrected Linux multilib toolchain (by @jimfangx in 157dd69e).
• Updated FireSim's U250 build-script selection for different Vivado releases and refreshed the AWS F2 HDK pin.
• Updated the remaining submodule pins for the 1.15.0 release (by @jimfangx in 98437c41).

Full Changelog

Full Changelog: 1.14.0...157dd69e

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Generators & Submodule updates

FireSim

Bump to: e1bdea8b

• Added FPGA shells, Golden Gate configurations, build/deployment support, and getting-started guides for Corigine MimicTurbo GT and Xilinx Alveo V80 (by @raghav-g13 in firesim/firesim#1890 and #1892).
• Added QSFP support for Corigine MimicTurbo GT (by Ethan Gao @doihead in firesim/firesim#1900).
• Added FPGA-managed bridge-stream DMA into host memory over PCIM on AWS F2 (by @iansseijelly in firesim/firesim#1894).
• Added and corrected FASED memory configurations, including 8 GiB/64 GiB layouts and FRFCFS configurations. Fixed banked LLC indexing and response handling to prevent lost responses and hangs (by @angelacu1, @jkjkim, and @Ferran-Hermida-Rivera).
• Improved on-premises FPGA enumeration and programming, added the RUNTIME_OPTIMIZED strategy, and kept LoadMemWriter bursts within 4 KiB AXI boundaries (by @raghav-g13 in firesim/firesim#1889).
• Added local execution of build-host commands and rsync operations when the build host is localhost (by @Ferran-Hermida-Rivera in firesim/firesim#1893).
• Added Corigine Vivado 2024.2 support and U250 block-design script selection by Vivado version (by @Ferran-Hermida-Rivera in firesim/firesim#1895 and @jimfangx in ebe8df3cc).
• Fixed Fab Classic/Paramiko installation to preserve the Conda cryptography dependency, and improved manager keepalives, logging-error handling, and metasimulation memory sizing (by @jimfangx and @iansseijelly in firesim/firesim#1888 and #1891).
• Restricted FireSim security-group ingress (by @Ferran-Hermida-Rivera in firesim/firesim#1899).

Rocket-Chip

Bump to: ece7b9ad

• Tied off the vector unit's FP request/response port when a tile has no scalar FPU, allowing that independently selectable configuration to elaborate (by @cwssemi in chipsalliance/rocket-chip#3824).

BOOM

Bump to: ba03175e

• Added BOOM v3 PMU event registration, per-tile event manifests, and optional memory-mapped tile counters. Registered 19 events spanning retirement, dispatch, branch redirects, cache/TLB activity, cycles, and dispatch stalls (by @iansseijelly in riscv-boom/riscv-boom#817).
• Added Tacit tracing support (by @iansseijelly in riscv-boom/riscv-boom#757).
• Denied normal hart accesses to Debug Module addresses while preserving Debug Mode access (by @KnightGOKU in riscv-boom/riscv-boom#805).
• Fixed issue-unit wiring and issue-queue ordering, including a matrix issue-queue program-order inversion and Large+BOOM elaboration problems (by Tianrui Wei @tianrui-wei and @iansseijelly in riscv-boom/riscv-boom#804, #756, and #748).
• Gated memory exceptions during DTLB misses so invalid TLB results cannot raise exceptions (by @Ferran-Hermida-Rivera in riscv-boom/riscv-boom#789).
• Prevented a page-table-walk response from committing and dropping a nacked store (by Tianrui Wei @tianrui-wei in riscv-boom/riscv-boom#787).
• Fixed the HellaCache response index assignment and made the default GigaBOOM fetch-buffer size divisible by decode width (by @Jeremy-Jia in riscv-boom/riscv-boom#760 and #761).
• Adjusted execution/data-cache assertions and widened the store-conditional failure debug counter (by @jimfangx and @Ferran-Hermida-Rivera in riscv-boom/riscv-boom#774).

PMU

New submodule: 079b96f7

• Added a Chisel PMU library with a per-tile event registry, event-list schema, counter bank, and TileLink register interface (by @iansseijelly).
• Added bare-metal C headers, a platform-header generator, documentation, and unit tests.

Rocket Chip Inclusive Cache

Bump to: 27df9284

• Used BigInt for control addresses, allowing addresses at 0x80000000 and above (by @tynan-jdwk in chipsalliance/rocket-chip-inclusive-cache#44).
• Added a TileLink crossing between the control bus and cache control ports (by @tynan-jdwk in chipsalliance/rocket-chip-inclusive-cache#42).

testchipip

Bump to: 555ff3fb

• Allowed cosimulation targets to supply their device map, custom CSRs, and register widths (by @Ferran-Hermida-Rivera in ucb-bar/testchipip#277).
• Corrected trap-vector comparisons and took interrupt-pending CSR values from the DUT when Spike has no CLINT.
• NaN-boxed Spike FP registers at reset and ignored NaN payload differences in write-data comparisons.
• Added machine-state and DUT trap-cause dumps on cosimulation divergence.
• Fixed signed overflow in source-ID arithmetic for multi-chiplet simulation (by @Rakanic in ucb-bar/testchipip#276).

Saturn Vectors

Bump to: 8c5115c1

• Added useVectorFP and INTV256D128RocketConfig for integer-only vectors. The generated ISA description reflects the selected vector capabilities, and integer-only configurations reject vector FP encodings, including those hosted in integer units (by @cwssemi in ucb-bar/saturn-vectors#100).
• Fixed vsmul saturation bounds at SEW=64, including incorrect clipping and spurious vxsat updates caused by Scala integer overflow (by @cwssemi in ucb-bar/saturn-vectors#98).
• Fixed store-segment buffer advancement after page splits, preventing skipped fields and store-path livelocks (by @cwssemi in ucb-bar/saturn-vectors#97).
• Fixed unsigned immediate handling for vsll.vi, vsra.vi, vssra.vi, and vror.vi, and corrected rotate direction/signedness for high vror.vi immediates (by @cwssemi in ucb-bar/saturn-vectors#94).
• Corrected scalar operand truncation/extension for vmulhu.vx, vmulhsu.vx, and vwmulu.vx (by Emilien Garnier @emiliengnr in ucb-bar/saturn-vectors#90).
• Corrected scalar operand extension for vdivu.vx and vremu.vx (by Emilien Garnier @emiliengnr in ucb-bar/saturn-vectors#87).
• NaN-boxed narrow scalar FP operands in .vf instructions (by Emilien Garnier @emiliengnr in ucb-bar/saturn-vectors#88).

FPGA Shells

Bump to: a4823d36

• Added Genesys 2, Nexys Video, and ZCU104 board support (by Vladimir Milovanović @milovanovic in chipsalliance/rocket-chip-fpga-shells#35, #34, and #33).

FireMarshal

Bump to: 61fae80f

• Updated Linux to 6.16 and refreshed the FireSim block/network drivers (by @iansseijelly in firesim/FireMarshal#323).
• Updated Buildroot, BusyBox integration, and OpenSBI for the newer toolchains; corrected boot-image dependency tracking and OpenSBI payload/device-tree placement (by @jimfangx in firesim/FireMarshal#327).
• Restored Buildroot and BusyBox ABI configuration defaults with the fixed scalar/vector Linux multilib toolchain, including cleanup of outputs built with the former forced lp64 setting (by @jimfangx in 61fae80f).
• Added --lspOnly support to generate kernel compilation commands for editor tooling (by @iansseijelly in firesim/FireMarshal#321).

Software Workloads and Toolchain Collateral

• Bumped CoreMark to 4aa835c7, updating riscv-coremark and fixing the bare workload configuration name (by @raghav-g13 in ucb-bar/coremark-workload#2).
• Bumped Baremetal-IDE to 0eb41e63, including LLVM toolchain support and PWM/build updates.
• Bumped libgloss to 177ce07d, fixing multilib configurations to include CSR support (by @jimfangx in ucb-bar/libgloss-htif#15).
• Bumped the proxy kernel to 9c61d298, including GCC 15 build fixes, device-tree linker placement, syscall additions, and RV32 floating-point helper fixes.