SystemVerilog-Practice

Averager for N number of inputs, Average output is given after N number of clock cycle with Valid
Parametric Bubble sort and Test-Bench

Name		Name	Last commit message	Last commit date
Latest commit History 18 Commits
README.md		README.md
averager.sv		averager.sv
bubble_sort.sv		bubble_sort.sv
bubble_sort_tb.sv		bubble_sort_tb.sv
credit_cntr.sv		credit_cntr.sv
indexofone.sv		indexofone.sv
indexofone_tb.sv		indexofone_tb.sv
max2bitsetseq.sv		max2bitsetseq.sv
max2bitsetseq_optim.sv		max2bitsetseq_optim.sv
max2bitsetseq_optim_tb.sv		max2bitsetseq_optim_tb.sv
max2bitsetseq_tb.sv		max2bitsetseq_tb.sv
onepriotworoundarb.sv		onepriotworoundarb.sv
onepriotworoundarb_tb.sv		onepriotworoundarb_tb.sv
parametric_mux.sv		parametric_mux.sv
rdy_val_buffer.sv		rdy_val_buffer.sv
rdy_valid_slave.sv		rdy_valid_slave.sv
req_ack_2ph_rx.sv		req_ack_2ph_rx.sv
req_ack_2ph_tx.sv		req_ack_2ph_tx.sv
req_ack_4ph_rx.sv		req_ack_4ph_rx.sv
req_ack_4ph_tx.sv		req_ack_4ph_tx.sv
ringcounter_jerky.sv		ringcounter_jerky.sv
ringcounter_jerky_tb.sv		ringcounter_jerky_tb.sv
ser2par.sv		ser2par.sv
ser2par_tb.sv		ser2par_tb.sv
serbcdtox3.sv		serbcdtox3.sv
serbcdtox3_tb.sv		serbcdtox3_tb.sv
shiftaddmul.sv		shiftaddmul.sv
shiftaddmul_tb.sv		shiftaddmul_tb.sv
skippedmul3count.sv		skippedmul3count.sv
skippedmul3count_tb.sv		skippedmul3count_tb.sv
streamInverse.sv		streamInverse.sv
streamInverse_tb.sv		streamInverse_tb.sv
sync_fifo.sv		sync_fifo.sv
width_convert_hi2lo_rdy_val.sv		width_convert_hi2lo_rdy_val.sv

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