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JAMIA-RISC-V
JAMIA-RISC-V PublicForked from devchadha-jmi/JAMIA-RISC-V
JAMIA-RISC-V Core is a three stage pipelined general purpose processor written in Verilog using RV32I ISA.
Verilog
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FIR-and-IIR-using-Verilog-and-HLS
FIR-and-IIR-using-Verilog-and-HLS PublicForked from devchadha-jmi/FIR-and-IIR-using-Verilog-and-HLS
This repository carries the design of FIR and IIR based Low Pass Filter, designed using Verilog and HLS
JavaScript
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