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1. 4bit-pattern-detector 4bit-pattern-detector Public

   4-bit pattern detector in Verilog with FSM. Detects user-defined patterns in serial input, supports overlapping matches, and runs synchronously. Includes testbench for verification. Showcases Veril…

   Verilog

2. 6bit-rate-limiter-verilog 6bit-rate-limiter-verilog Public

   Verilog implementation of a 6-bit rate limiter with synchronous reset and adjustable step size, including a testbench for verification.

   Verilog