Tiny Tapeout Verilog Project Template

A variant for the Verilog Meetup community

This template has the following changes on the top of the base ttsky-verilog-template.

1. It instantiates lab_top module inside project.v. lab_top is used to abstract FPGA boards in BGM a.k.a. basics-graphics-music project.

2. Instantiates and adds glue logic for the controller of the TM1638 board interface. This peripheral board features 8 buttons, 8 LEDs and 8-digit 7-segment indicator. It is used in BGM project as an add-on for FPGA boards that have insufficient number of LEDs/buttons/7-segment digits for the lab examples in BGM package.

3. Adds glue logic to make the design compatible with Tiny VGA used in TT10 Demoscene projects.

4. Instantiates and adds glue logic for the controller of the I2S interface for the INMP441 microphone.

5. Adds some code to bypass Python-based cocotb testbench and do all verification in SystemVerilog.

6. Adds hooks to the documentation and other text files to make use of the template easier. Just grep for TODO.

Credits

Yuri Panchul and Verilog Meetup, with contributions from:

• TM1638 interface module support, based on Alan Garfield's implementation: Alexander Kirichenko, Ruslan Zalata and Anton Malakhov.

• Sound recognition with INMP441 microphone: Victor Prutyanov and Vadim Ostrikov.

• Other contributors to the basics-graphics-music (BGM) project.

Below is the original text from the Tiny Tapeout GitHub repository.

Tiny Tapeout Verilog Project Template

• Read the documentation for project

What is Tiny Tapeout?

Tiny Tapeout is an educational project that aims to make it easier and cheaper than ever to get your digital and analog designs manufactured on a real chip.

To learn more and get started, visit https://tinytapeout.com.

Set up your Verilog project

1. Add your Verilog files to the src folder.
2. Edit the info.yaml and update information about your project, paying special attention to the source_files and top_module properties. If you are upgrading an existing Tiny Tapeout project, check out our online info.yaml migration tool.
3. Edit docs/info.md and add a description of your project.
4. Adapt the testbench to your design. See test/README.md for more information.

The GitHub action will automatically build the ASIC files using LibreLane.

Enable GitHub actions to build the results page

• Enabling GitHub Pages

Resources

• FAQ
• Digital design lessons
• Learn how semiconductors work
• Join the community
• Build your design locally

What next?

• Submit your design to the next shuttle.
• Edit this README and explain your design, how it works, and how to test it.
• Share your project on your social network of choice:
  • LinkedIn #tinytapeout @TinyTapeout
  • Mastodon #tinytapeout @matthewvenn
  • X (formerly Twitter) #tinytapeout @tinytapeout
  • Bluesky @tinytapeout.com