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Merged
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Yosys+Odin #1798
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d89eaaa
[Infra]:- Adding FAILED status for generating yosys blifs
sdamghan 666bcf5
[Odin]: - Resolving logical nodes
sdamghan 89097ec
[Odin]: - fixing bug for adders in blif_elaborate
sdamghan 6c29786
[Odin]: - Adding support for $dffe sub-circuit
sdamghan 525d3fc
[Odin]: - Adding attribute structure for netlist nodes
sdamghan 26627fd
[Odin]: Chaniging the operation type MULTI_BIT_MUX2 to MULTI_PORT_BIT…
sdamghan be18d4a
[Odin]: Adding multiport n-bit multiplexer elaborator
sdamghan 1753b63
[Odin]: freeing attribute structure in netlist free function
sdamghan f1651dd
[Odin]: Adding multiport nbits multiplexer (MULTIPORT_nBIT_MUX)
sdamghan 43f365e
[Infra]: Adding yosys failure logs for benchmarks
sdamghan e006d28
[Odin]: - Adding support for $adffe sub-circuit
sdamghan dafdb81
[Odin]: Adding support for $lt, $le, $gt and $ge sub-circuits
sdamghan d8daadb
[Infra]: Adding separate _VERILOG directory for modified verilog for …
sdamghan 6504580
[Odin]: - Adding support for $mul sub-circuit
sdamghan d5d3538
[Odin]: Adding support for $eqx and $nex sub-circuits
sdamghan 4233bfc
[Odin]: Adding support for $logic_and and $ne sub-circuits
sdamghan 7b9f2f3
[Odin]: Adding support for $shl, $shr, $sshl and $sshr sub-circuits
sdamghan 71f977d
[Odin]: fixing subtraction freeing node bug
sdamghan 712591c
[Odin]: Fixing subtraction memory leaks
sdamghan a8729d8
[Odin]: Adding support for $neq subscircuit
sdamghan 715d255
[Odin]: - Fixing mem leakw
sdamghan 38ab5e7
[Odin]: adding resolve_add_node and removing check_block_ports
sdamghan 0cce221
[Odin]: Mixing NEG and MINUS circuits
sdamghan f4f7374
[Odin]: adding resolve_arithmetic_node for ADD, MINUS and MULTIPLY
sdamghan a1aaf48
[Odin]: - Adding support for $div sub-circuit
sdamghan 97c72b4
[Odin]: Adding subtraction with borrow in/out in partial mapping
sdamghan 9f7d7fe
[Odin]: - fixing divison and subtraction bugs
sdamghan 4c66da4
[Infra]: - Adding generate_blif option to verify_odin script
sdamghan 28b6728
[Odin]: - Adding support for $mod subcircuit
sdamghan c0e9291
[Odin]: - Adding support for $dlatch, $adlatch, and $adff subcircuits
sdamghan fb67b46
[Odin]: - Adding constant multipication
sdamghan a055c55
[Odin]: connceting const multiplier output connection
sdamghan 96f3560
[Infra]: Updating all expectation results
sdamghan 8b63e04
[Infra]: - Fixing directory iteration in run_yosys script for suites
sdamghan 7730f44
[Odin]: Modify GTE, LTE, GT and LT circuits
sdamghan 5c34331
[Infra]: Adding techmap full benchmarks to regreesion test
sdamghan ec69a82
[Odin]: fixing constant multiplier output sizes
sdamghan 0a15961
[Odin]: fixing the subtraction conflict.
sdamghan 43678d7
[Odin]: equalize the size of logical nodes' input ports
sdamghan aa55dfe
[Infra]: - Adding techmap full testing suite
sdamghan 0ef7bd1
[Infra]: - Adding primitives modules (vtr_flow/primitives.v) as a lib…
sdamghan 6662d2f
[Odin]: - Adding support for VTR primitives
sdamghan 2c88008
[Odin]: - Adding techmap support for dual_port_ram
sdamghan f65ea40
[Infra]: reformatiing the regression_test/_BLIF
sdamghan fbcfaed
[Odin]: synchronize the clock port name in primitives, ODIN_II source…
sdamghan efc77de
[Odin]: - adding support for $dffsre sub-circuit
sdamghan 2c3bbf7
[Odin]: - adding support for $mem (read write memory) in yosys blif
sdamghan e5f2ad4
[Odin]: - adding support for $pow sub-circuit
sdamghan cb22ed8
[Odin]: seperating case_equal functions from blif_elaborate
sdamghan 11ee8e4
[Odin]: formating codes
sdamghan b58d1bb
[Odin]: adding support for constant exponentation
sdamghan 55012c4
[Odin]: fixing the simulation bug for memory hard blocks
sdamghan e3ad182
[Odin]: fixing the BRAM clock signal simulation issue
sdamghan ea71351
[Infra]: regenerating expectation results
sdamghan a4ec289
[Odin]: - fixing dual write port bug for DPRAM and BRAM blocks
sdamghan 0535ef3
[Odin]: - fixing undriven multiplier output pins
sdamghan 552c0ae
[Odin]: - adding support for $sdffce sub-circuit
sdamghan dc8ae2e
[Odin]: - fixing over-freeing the constant multipication internal sig…
sdamghan 9dada91
[Odin]: fixing throw exception for mismatching hard block port sizes …
sdamghan f929b05
[Odin]: - separating block memories and read only memories elaboration
sdamghan 12d5511
[Infra]: Adding pmuxtree phase to yosys tcl script to resolve pmux su…
sdamghan 94f5577
[Odin]: - adding support for mapping the read only memories and block…
sdamghan b99a0d4
[Infra]: regenerating new expectation results
sdamghan 217c0ee
[Odin]: - adding threshold for LUTRAM inference
sdamghan 034f9fa
[Odin]: - adding the Verilog Class to design
sdamghan 96db6f6
[Infra]: - adding techmap large benchmark to regression suite for tec…
sdamghan a0a4053
[Odin]: Adding support for $sr sub-circuit
sdamghan 42e3c2c
[Infra]: removing undriven signals from blif file using opt -undriven
sdamghan 8a5585e
[Infra]: - fixing large benchmarks syntax errors
sdamghan c3fff2b
[Infra]: fixing task name in run_yosys and creating benchmark folder …
sdamghan 3b4e861
[Infra]: - adding a techmap task for VTR benchmarks
sdamghan 3661761
[Odin]: - fixing clock connectivity of arst flip flops (adff and adffe)
sdamghan 4c132ce
[Odin]: refining the flip flop desings to optimize the final netlist
sdamghan 3f96142
[Odin]: refining the spram and dpram inferrence
sdamghan ec432d5
[Infra]: organizing tasks with sub-folders in blif generation process…
sdamghan 5cba585
[Infra]: changing large benchmarks to fix uninitialized reg errors
sdamghan 9227282
[Infra]: considering relative path to BLIF directory in blif generati…
sdamghan b92063e
[Infra]: avoiding yosys to convert memory blocks to list of registers
sdamghan 61e6069
[Infra]: - copying the single port RAM and Dual port RAM modules in v…
sdamghan 793a021
[Infra]: adding new task for modified VTR benchmarks
sdamghan f325864
[Infra]: fixing hard block RAM errors for Modified VTR benchmark
sdamghan 19c49d1
[Odin]: decoding output signal of dpram inferred from block memories …
sdamghan dc70717
[Odin]: Memory blocks and ROMs will be mapped only in one of the foll…
sdamghan 96c6e58
[Odin]: fixing ROM->2R DPRAM clk connectivity
sdamghan 9cf666c
[Odin]: - adding mem id to dpram, spram created from block memories
sdamghan 16ac9e5
[Odin]: adding block memories 2r(spram) and 2rw(dpram) mapping
sdamghan 63c5335
[Infra]: - removing simulation for large and modified VTR benchmark
sdamghan 6922068
[Infra]: regenerating common expectation results
sdamghan 956a984
[Odin]: removing spram from dpram list for optimization iteration
sdamghan 555970a
[Odin]: splitting block memories in depth if needed in the case of im…
sdamghan dffd21a
[Infra]: - the depth variable in both_ram.v has changed due to the lo…
sdamghan 7793f2a
[Infra]: regenerating new expectation results for micro benchmarks
sdamghan 6a6078e
[Infra]: regenerating new expectation results for techmap operator be…
sdamghan 35a0972
[Infra]: regenerating new expectation results for techmap full benchmark
sdamghan 9d7715c
[Odin]: adding a new name convention for .cc files
sdamghan aa58963
[Infra]: - modifying arch files for tasks in techmap_suite
sdamghan 5862f32
[Infra]: - modifying full and modifid vtr benchmark to include defaul…
sdamghan 96a7ca3
[Infra]: adding missed yosys blif files for keywords tech suite
sdamghan fb7a870
[Infra]: adding techmap fpu/softlogic benchmarks to techmap
sdamghan 8fed3ce
[Odin]: changing the variable name (signals) to avoid warnings in C++…
sdamghan 6e17d21
[Infra]: adding fpu/softlogic blif files
sdamghan d577656
[Odin]: removing unused external declartion in memories.h
sdamghan 1be70cb
[Infra]: removing blif file to avoid git lfs warnings
sdamghan 6ca3649
[Odin]: - adding coarsen blif cleanup
sdamghan 5248c8b
[Odin]: fix netlist vcc, gnd and pad names memory leak
sdamghan f768480
[Odin]: fixing memory leaks (pin->mapping)
sdamghan 06a7904
[Odin]: fixing sanitizer leaks
sdamghan 3760997
[infra]: regenerating new expectation results for techmap keywords be…
sdamghan 54d6ccf
[Odin]: - moving bitset usage inside constant creation function
sdamghan 128b771
[Odin]: fixing sanitizer error related to quotient pin mem leak
sdamghan dff33ab
[Odin]: - fixing mod pin leak error
sdamghan 7312272
[Odin]: - fixing pad signals list memory leak in block memories
sdamghan 5361934
[Infra]: regenerating new expectation results for techmap micro bench…
sdamghan cc65ad5
[Odin]: - optimization: reducing memory block address width based on …
sdamghan 645459a
[Odin]: constant multipication port size reducation for useless pins
sdamghan 0b224b6
[Infra]: adding full flag for yosys optimization
sdamghan c30a86a
[Odin]: - adding constant shift implementation to partial mapping to …
sdamghan e0f3841
[Infra]: regenerating new expectation results
sdamghan 53af6f2
[Odin]: formatting the code style
sdamghan c5b7e2d
[Odin]: fixing multiliers memory leak while Odin runs with verilog files
sdamghan 0e19fa6
[Odin]: resolving memory leaks and segfault resulted by BUF_NODE
sdamghan 7761e66
[Odin]: Adding cin pin to add and sub sub-circuits when adder hard bl…
sdamghan 5eed51d
[Odin]: - fixing subtraction input pins leak while using arch with ha…
sdamghan d6eeee3
[Infra]: - regenerating _BLIF/syntax new expectation results using sa…
sdamghan e9b03b1
[Odin]: fixing $reduce_and sub-circuit inference
sdamghan bf570bd
[Infra]: - regenerating _BLIF/full new expectation results using sani…
sdamghan e84d848
[Odin]: fixing mem leak for related_ast_node for ram blocks
sdamghan 11f2816
[Infra]: - adding default arg for modified VTR benchmarks
sdamghan 145e544
[Infra]: removing extra verilog files for techmap regression tests
sdamghan 8a0005c
[Infra]: fixing adding duplicate blif files generated run_yosys.sh
sdamghan 1e7fffe
[Odin]: fixing segfault for traversing backward if a pin is undriven
sdamghan 140d40e
[Odin]: fixing segfault resulteb by freeing a buf node if the buf nod…
sdamghan 1400f1a
[Odin]: fixing blif_writer pointer mem leak
sdamghan ea15e4d
[Odin]: fixing overfreeing pad_string in the case of unconnected inputs
sdamghan 8eedcac
[Odin]: padding nets without drivers with PAD instead of GND to avoid…
sdamghan e538b05
[Odin]: avoiding reordering vcc and gnd net pins (partial map travers…
sdamghan 2c18f8e
[Infra]: updating lightsuite expectation results with new output stat…
sdamghan 83f4cee
[Infra]: updating heavy_suite expectation results with new output sta…
sdamghan c0db806
[Infra]: regenerating techmap_suite expectation results using sanitizer
sdamghan 244877b
[Odin]: formating code
sdamghan c245fa5
[Odin]: avoiding segfault for net visualizer (null pointer for remove…
sdamghan 1e6d5f7
[Infra]: - building yosys in odin_reg_techmap CI test
sdamghan 50b1e74
[Infra]: - generating yosys BLIF file when techmap suite is called
sdamghan 7d842ec
[Infra]: - generating yosys blif IF the benchmarks blif do not exist
sdamghan f98eae0
[Infra]: - improving run_yosys.sh help function
sdamghan 5066a9c
[Infra]: generating yosys blif files for run_reg_test/odin_reg_techma…
sdamghan 9cf01e8
[Vtrutil]: adding getline with comment igorance (compatible with both…
sdamghan d6fa091
[Odin]: adding getbline to read BLIFs according to line styles (getli…
sdamghan 80f2865
[CI]: adding odin_tech_basic and odin_tech_strong
sdamghan 7a3663a
[Odin]: - fixing netlist identifier mem leak if blif file is empty
sdamghan 24cb5be
[Odin]: - fixing clang non-trival type passing error
sdamghan 6b5320b
[Infra]: - regenerating _BLIF/full expectation results
sdamghan 6c66d1d
[Infra]: command arg to run a single benchmark in run_yosys script
sdamghan ae3a9c8
[Odin]: cleaning up the old soft mult node after splitting
sdamghan 91e2a40
[Odin]: driving undriven nets with ZEROs
sdamghan a056e42
[Flow]: updating mult_consts golden results
sdamghan deca3dc
[Flow]: fixing undriven hard block clk pin in koios/attention_layer
sdamghan 6006d32
[Infra]: Adding odin_tech_strong to kokoro
sdamghan 30ef96c
[Odin]: pruning extra pad pins from yosys generated subtraction node
sdamghan 59c6a17
[Odin]: fix create constant signal list indexing
sdamghan b8e0478
[Odin]: fixing asynchrounous dffs connectivities
sdamghan 5325762
[Odin]: - spliting logical nodes in single bit logical nodes
sdamghan d959a64
[Odin]: - removing unused constant shift operand pins
sdamghan d57be5f
[Odin]: fix equalize subtraction ports bug
sdamghan a58ff8e
[Infra]: - removing fine grain optimiztion in synth tcl script
sdamghan 232e9c4
[Odin]: fixing simulation mismatch
sdamghan 6f9dd2f
[Odin]: - checking addr port equality for BRAMs
sdamghan 3762d8f
[Odin]: - extra logiccal node outputs are driven with PAD node
sdamghan 8152a30
[Odin]: - adding pure const binary operation
sdamghan 1d5b12d
[Odin]: perform logical node optimization
sdamghan 6504348
[Odin]: - removing OR chain for memories enables
sdamghan 6c49b68
[Odin]: regenerate techmap_lightsuite expectation results
sdamghan dfd6bf6
[Odin]: removing checking a stage before mem blocks for matching ports
sdamghan f5cbd90
[Odin]: separating one-hot mux_2 with mux_2 with single selector (SMU…
sdamghan 72c4c00
[Odin]: reformat ff structures with smux_2
sdamghan d4aa7c9
[Odin]: improve various ff inference and tide-up Flipflop .cc file
sdamghan 8a267ba
[Odin]: regenerate techmap_lightsuite expectation results
sdamghan 1c051ae
[Odin]: adding nr/nrnw support using muxed read/write ports
sdamghan 4b19e72
[Odin]: improving area of shift circuits by instantiating mux with si…
sdamghan e7b084c
[Odin]: Update techmap_light suite expectation results
sdamghan 25a59cb
[Odin]: updatnge expectation results
sdamghan ee4be90
[Odin]: - refomart the input section for odin xml config file
sdamghan b8ddcfc
[Infra]: adding vtr task for modified vtr benchmarks running by yosys…
sdamghan cf0d42e
[Odin]: - resolve asynchronous dff to formal one by Yosys
sdamghan 741f613
[Odin]: adding Odin techlib for BRAM and ROM
sdamghan 91b6cf1
[Odin]: adding ymem sub-circuit
sdamghan 62747fb
[Odin]: - adding -o option to run_yosys
sdamghan a7f63bf
[Odin]: fix segfault for large npbMUXes
sdamghan a3ddaf9
[Odin]: fix clock node counting during blif elaboration
sdamghan 3cc3ab7
[Odin]: regenerating techmap expectation results
sdamghan 610d8e1
[Odin]: adding fflegalize option to make all FF rising edge
sdamghan a7bb75e
[Odin]: - adding storing yosys log option to run_yosys
sdamghan 1a5cad0
[Odin]: adding review comments
sdamghan 4806a2e
[Odin]: - adding file-scope comments
sdamghan 4d53169
[Odin]: reformat instantiation of subtraction with borrow signals
sdamghan 028a127
[Odin]: regenerating techmap expectation results
sdamghan 882ae3f
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
sdamghan 78f3cbb
[Odin]: make format
sdamghan 3398af4
[Odin]: removing extra spram/dpram module definitions in benchmarks hdl
sdamghan 535ae8f
[Odin]: - fixing SPRAM/DPRAM verificatory bug
sdamghan ca76b4a
[Odin]: integrate Yosys elaborator inside Odin-II
sdamghan 934a40b
[Odin]: - fix run_yosys and verify odin bug
sdamghan 1f1d473
[Odin]: reformat yosys+odin task files
sdamghan 6045eba
[Odin]: fix custom SP/DP RAM names read by BLIFReader
sdamghan eca67a1
[Odin]: move _VERILOG to verilog/yosys_compatible_verilogs
sdamghan 23ee3af
[Odin]: refactor techmap_light suite, FIR and full benchmarks for yos…
sdamghan d302dcc
[Odin]: - refactoring techmap_heavysuite for yosys+odin
sdamghan b27c8ae
[Odin]: - update techmap expectations
sjkelly 6f00613
[Odin]: - fix get_root_directory bug
sdamghan 425a47e
[Infra]: - create a new GitHub action job for vtr_reg_Yosys+Odin and …
sdamghan d36ddc2
[Infra]: adding yosys as a submodule to VTR repo
sdamghan d8b6a0d
[Odin]: fix swept pins for sdffce
sdamghan 3f005ce
[Infra]: adding a new Kokoro test for Yosys+Odin VTR reg test
sdamghan 2a2f74c
[Infra]: - remove yosys submodule
sdamghan aa17192
Squashed 'yosys/' content from commit b96eb888c
sdamghan c8c3cfc
Merge commit 'aa17192b7b70640a19f9aa3482f9dcdab1b52ae1' as 'yosys'
sdamghan bcfeda4
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
sdamghan 6ec6ca8
[Infra]: update Koios benchmarks with yosys-compatible version
sdamghan 36ef369
[Infra]: fix VTR and fpu/softlogic benchmarks errors
sdamghan 1bda319
[Odin]: - fix VTR, Koios and fpu task files for Odin verification script
sdamghan 0f8687a
[Odin]: - set Yosys executable path to the VTR/yosys
sdamghan 9944bcd
[Infra]: add yosys to EXTERNAL libs
sdamghan 5acc967
[Infra]: - add CMakeList.txt to libyosys
sdamghan 926c927
[Infra]: add "-DODIN_USE_YOSYS=ON" to config files of GitHub action a…
sdamghan 6954a87
[Odin]: - call Yosys in a fork process to handle Yosys failure
sdamghan cb9bb43
[Odin]: - add Yosys+Odin-II common benchmarks with Odin-II benchmarks
sdamghan b5e041d
[Odin]: - merge Yosys+Odin-II operator benchmarks with Odin-II operar…
sdamghan eada456
[Odin]: - merge Yosys+Odin-II FIR benchmarks with Odin-II FIR benchmarks
sdamghan ec882bf
[Odin]: - merge Yosys+Odin-II syntax benchmarks with Odin-II syntax b…
sdamghan 0119d26
[Odin]: - merge Yosys+Odin-II micro benchmarks with Odin-II micro ben…
sdamghan a8d3c29
[Odin]: - merge Yosys+Odin-II full benchmarks with Odin-II full bench…
sdamghan 6128b36
[Odin]: - merge Yosys+Odin-II large benchmarks with Odin-II large ben…
sdamghan dfff7ca
[Odin]: - merge Yosys+Odin-II preprocessor and c_functions benchmarks…
sdamghan 46cc609
[Odin]: merge Odin-II keyword suite with Yosys+Odin-II
sdamghan 5801a1c
[Odin]: - mkDelayWorker syntax error in Odin-II
sdamghan ba34a7a
[Odin]: fix verify_script bug for simulation vector posfix detection
sdamghan 9c86160
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
sdamghan d779c50
[Odin]: - regenerate expectation results of arch_sweep benchmarks
sdamghan 34c3c69
[Odin]: - add a review comment for unused_node cutoff in Odin-II netl…
sdamghan 35acb0c
[Infra]: invert yosys+odin changes to vtr_flow/benchmarks
sdamghan 40f0d37
[Infra]: make VTR benchmarks compatible with Yosys+Odin
sdamghan 3e86cda
[Infra]: - regenerate vtr_reg_yosys_odin golden results
sdamghan 4cb3b2f
[Odin]: - fix invalid mux decoder indexing
sdamghan abbd702
[Infra]: update vtr_reg_nightly_test3 and vtr_reg_nightly_test1/power…
sdamghan 0bef7ed
[Odin]: - fix Odin-II's techmap flow codebase format
sdamghan 34b994f
[Infra]: generate vtr_reg_yosys_odin golden results
sdamghan 446f5be
[Odin]: add -S/--tcl option to run Yosys in Odin-II
sdamghan 2d6e53a
[Odin]: - fix mkDelayWorker32B and mcml dpram sizes bug in Odin/VTR b…
sdamghan 6bff4a4
Merge branch 'master' into yosys+odin
vaughnbetz 3e581f7
Updated mcml output count for golden_results of vtr_reg_qor_chain_pre…
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,61 @@ | ||
# Format: //devtools/kokoro/config/proto/build.proto | ||
# Odin_tech_strong test checks the Odin-II technology mapping for | ||
# Yosys+Odin-II over Odin-II techmap_heavysuite (excluding ABC and VPR) | ||
|
||
build_file: "vtr-verilog-to-routing/.github/kokoro/run-vtr.sh" | ||
|
||
# 12 hours | ||
timeout_mins: 720 | ||
|
||
action { | ||
define_artifacts { | ||
# File types | ||
regex: "**/*.out" | ||
regex: "**/vpr_stdout.log" | ||
regex: "**/parse_results.txt" | ||
regex: "**/qor_results.txt" | ||
regex: "**/pack.log" | ||
regex: "**/place.log" | ||
regex: "**/route.log" | ||
regex: "**/*_qor.csv" | ||
strip_prefix: "github/vtr-verilog-to-routing/" | ||
} | ||
} | ||
|
||
env_vars { | ||
key: "KOKORO_TYPE" | ||
value: "continuous" | ||
} | ||
|
||
env_vars { | ||
key: "KOKORO_DIR" | ||
value: "vtr-verilog-to-routing" | ||
} | ||
|
||
env_vars { | ||
key: "VTR_DIR" | ||
value: "vtr-verilog-to-routing" | ||
} | ||
|
||
#Use default build configuration | ||
env_vars { | ||
key: "VTR_CMAKE_PARAMS" | ||
value: "-DODIN_USE_YOSYS=ON" | ||
} | ||
|
||
env_vars { | ||
key: "VTR_TEST" | ||
value: "odin_tech_strong" | ||
} | ||
|
||
#Options for run_reg_test.py | ||
# -show_failures: show tool failures in main log output | ||
env_vars { | ||
key: "VTR_TEST_OPTIONS" | ||
value: "-show_failures" | ||
} | ||
|
||
env_vars { | ||
key: "NUM_CORES" | ||
value: "3" | ||
} |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
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@@ -0,0 +1,69 @@ | ||
# Format: //devtools/kokoro/config/proto/build.proto | ||
# vtr_reg_yosys_odin test runs the VTR benchmarks through | ||
# the entire VTR with Yosys+Odin-II as the first CAD tool | ||
|
||
build_file: "vtr-verilog-to-routing/.github/kokoro/run-vtr.sh" | ||
|
||
# 72 hours | ||
timeout_mins: 4320 | ||
|
||
action { | ||
define_artifacts { | ||
# File types | ||
regex: "**/*.out" | ||
regex: "**/vpr_stdout.log" | ||
regex: "**/parse_results.txt" | ||
regex: "**/qor_results.txt" | ||
regex: "**/pack.log" | ||
regex: "**/place.log" | ||
regex: "**/route.log" | ||
regex: "**/*_qor.csv" | ||
regex: "**/*.out.gz" | ||
regex: "**/vpr_stdout.log.gz" | ||
regex: "**/parse_results.txt.gz" | ||
regex: "**/qor_results.txt.gz" | ||
regex: "**/pack.log.gz" | ||
regex: "**/place.log.gz" | ||
regex: "**/route.log.gz" | ||
regex: "**/*_qor.csv.gz" | ||
strip_prefix: "github/vtr-verilog-to-routing/" | ||
} | ||
} | ||
|
||
env_vars { | ||
key: "KOKORO_TYPE" | ||
value: "continuous" | ||
} | ||
|
||
env_vars { | ||
key: "KOKORO_DIR" | ||
value: "vtr-verilog-to-routing" | ||
} | ||
|
||
env_vars { | ||
key: "VTR_DIR" | ||
value: "vtr-verilog-to-routing" | ||
} | ||
|
||
#Use default build configuration | ||
env_vars { | ||
key: "VTR_CMAKE_PARAMS" | ||
value: "-DODIN_USE_YOSYS=ON" | ||
} | ||
|
||
env_vars { | ||
key: "VTR_TEST" | ||
value: "vtr_reg_yosys_odin" | ||
} | ||
|
||
#Options for run_reg_test.py | ||
# -show_failures: show tool failures in main log output | ||
env_vars { | ||
key: "VTR_TEST_OPTIONS" | ||
value: "-show_failures" | ||
} | ||
|
||
env_vars { | ||
key: "NUM_CORES" | ||
value: "8" | ||
} |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,61 @@ | ||
# Format: //devtools/kokoro/config/proto/build.proto | ||
# Odin_tech_strong test checks the Odin-II technology mapping for | ||
# Yosys+Odin-II over Odin-II techmap_heavysuite (excluding ABC and VPR) | ||
|
||
build_file: "vtr-verilog-to-routing/.github/kokoro/run-vtr.sh" | ||
|
||
# 12 hours | ||
timeout_mins: 720 | ||
|
||
action { | ||
define_artifacts { | ||
# File types | ||
regex: "**/*.out" | ||
regex: "**/vpr_stdout.log" | ||
regex: "**/parse_results.txt" | ||
regex: "**/qor_results.txt" | ||
regex: "**/pack.log" | ||
regex: "**/place.log" | ||
regex: "**/route.log" | ||
regex: "**/*_qor.csv" | ||
strip_prefix: "github/vtr-verilog-to-routing/" | ||
} | ||
} | ||
|
||
env_vars { | ||
key: "KOKORO_TYPE" | ||
value: "presubmit" | ||
} | ||
|
||
env_vars { | ||
key: "KOKORO_DIR" | ||
value: "vtr-verilog-to-routing" | ||
} | ||
|
||
env_vars { | ||
key: "VTR_DIR" | ||
value: "vtr-verilog-to-routing" | ||
} | ||
|
||
#Use default build configuration | ||
env_vars { | ||
key: "VTR_CMAKE_PARAMS" | ||
value: "-DODIN_USE_YOSYS=ON" | ||
} | ||
|
||
env_vars { | ||
key: "VTR_TEST" | ||
value: "odin_tech_strong" | ||
} | ||
|
||
#Options for run_reg_test.py | ||
# -show_failures: show tool failures in main log output | ||
env_vars { | ||
key: "VTR_TEST_OPTIONS" | ||
value: "-show_failures" | ||
} | ||
|
||
env_vars { | ||
key: "NUM_CORES" | ||
value: "3" | ||
} |
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---|---|---|
@@ -0,0 +1,69 @@ | ||
# Format: //devtools/kokoro/config/proto/build.proto | ||
# vtr_reg_yosys_odin test runs the VTR benchmarks through | ||
# the entire VTR with Yosys+Odin-II as the first CAD tool | ||
|
||
build_file: "vtr-verilog-to-routing/.github/kokoro/run-vtr.sh" | ||
|
||
# 72 hours | ||
timeout_mins: 4320 | ||
|
||
action { | ||
define_artifacts { | ||
# File types | ||
regex: "**/*.out" | ||
regex: "**/vpr_stdout.log" | ||
regex: "**/parse_results.txt" | ||
regex: "**/qor_results.txt" | ||
regex: "**/pack.log" | ||
regex: "**/place.log" | ||
regex: "**/route.log" | ||
regex: "**/*_qor.csv" | ||
regex: "**/*.out.gz" | ||
regex: "**/vpr_stdout.log.gz" | ||
regex: "**/parse_results.txt.gz" | ||
regex: "**/qor_results.txt.gz" | ||
regex: "**/pack.log.gz" | ||
regex: "**/place.log.gz" | ||
regex: "**/route.log.gz" | ||
regex: "**/*_qor.csv.gz" | ||
strip_prefix: "github/vtr-verilog-to-routing/" | ||
} | ||
} | ||
|
||
env_vars { | ||
key: "KOKORO_TYPE" | ||
value: "presubmit" | ||
} | ||
|
||
env_vars { | ||
key: "KOKORO_DIR" | ||
value: "vtr-verilog-to-routing" | ||
} | ||
|
||
env_vars { | ||
key: "VTR_DIR" | ||
value: "vtr-verilog-to-routing" | ||
} | ||
|
||
#Use default build configuration | ||
env_vars { | ||
key: "VTR_CMAKE_PARAMS" | ||
value: "-DODIN_USE_YOSYS=ON" | ||
} | ||
|
||
env_vars { | ||
key: "VTR_TEST" | ||
value: "vtr_reg_yosys_odin" | ||
} | ||
|
||
#Options for run_reg_test.py | ||
# -show_failures: show tool failures in main log output | ||
env_vars { | ||
key: "VTR_TEST_OPTIONS" | ||
value: "-show_failures" | ||
} | ||
|
||
env_vars { | ||
key: "NUM_CORES" | ||
value: "8" | ||
} |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,6 +1,8 @@ | ||
regression_test/run* | ||
regression_test/benchmark/_BLIF | ||
regression_test/latest | ||
|
||
/yosys | ||
/temp | ||
/*.v | ||
/*.blif | ||
|
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