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d89eaaa
[Infra]:- Adding FAILED status for generating yosys blifs
sdamghan May 30, 2021
666bcf5
[Odin]: - Resolving logical nodes
sdamghan May 30, 2021
89097ec
[Odin]: - fixing bug for adders in blif_elaborate
sdamghan May 30, 2021
6c29786
[Odin]: - Adding support for $dffe sub-circuit
sdamghan May 30, 2021
525d3fc
[Odin]: - Adding attribute structure for netlist nodes
sdamghan May 31, 2021
26627fd
[Odin]: Chaniging the operation type MULTI_BIT_MUX2 to MULTI_PORT_BIT…
sdamghan May 31, 2021
be18d4a
[Odin]: Adding multiport n-bit multiplexer elaborator
sdamghan Jun 1, 2021
1753b63
[Odin]: freeing attribute structure in netlist free function
sdamghan Jun 1, 2021
f1651dd
[Odin]: Adding multiport nbits multiplexer (MULTIPORT_nBIT_MUX)
sdamghan Jun 1, 2021
43f365e
[Infra]: Adding yosys failure logs for benchmarks
sdamghan Jun 1, 2021
e006d28
[Odin]: - Adding support for $adffe sub-circuit
sdamghan Jun 1, 2021
dafdb81
[Odin]: Adding support for $lt, $le, $gt and $ge sub-circuits
sdamghan Jun 1, 2021
d8daadb
[Infra]: Adding separate _VERILOG directory for modified verilog for …
sdamghan Jun 1, 2021
6504580
[Odin]: - Adding support for $mul sub-circuit
sdamghan Jun 1, 2021
d5d3538
[Odin]: Adding support for $eqx and $nex sub-circuits
sdamghan Jun 1, 2021
4233bfc
[Odin]: Adding support for $logic_and and $ne sub-circuits
sdamghan Jun 1, 2021
7b9f2f3
[Odin]: Adding support for $shl, $shr, $sshl and $sshr sub-circuits
sdamghan Jun 2, 2021
71f977d
[Odin]: fixing subtraction freeing node bug
sdamghan Jun 2, 2021
712591c
[Odin]: Fixing subtraction memory leaks
sdamghan Jun 2, 2021
a8729d8
[Odin]: Adding support for $neq subscircuit
sdamghan Jun 2, 2021
715d255
[Odin]: - Fixing mem leakw
sdamghan Jun 2, 2021
38ab5e7
[Odin]: adding resolve_add_node and removing check_block_ports
sdamghan Jun 2, 2021
0cce221
[Odin]: Mixing NEG and MINUS circuits
sdamghan Jun 4, 2021
f4f7374
[Odin]: adding resolve_arithmetic_node for ADD, MINUS and MULTIPLY
sdamghan Jun 4, 2021
a1aaf48
[Odin]: - Adding support for $div sub-circuit
sdamghan Jun 5, 2021
97c72b4
[Odin]: Adding subtraction with borrow in/out in partial mapping
sdamghan Jun 6, 2021
9f7d7fe
[Odin]: - fixing divison and subtraction bugs
sdamghan Jun 7, 2021
4c66da4
[Infra]: - Adding generate_blif option to verify_odin script
sdamghan Jun 7, 2021
28b6728
[Odin]: - Adding support for $mod subcircuit
sdamghan Jun 7, 2021
c0e9291
[Odin]: - Adding support for $dlatch, $adlatch, and $adff subcircuits
sdamghan Jun 7, 2021
fb67b46
[Odin]: - Adding constant multipication
sdamghan Jun 8, 2021
a055c55
[Odin]: connceting const multiplier output connection
sdamghan Jun 8, 2021
96f3560
[Infra]: Updating all expectation results
sdamghan Jun 8, 2021
8b63e04
[Infra]: - Fixing directory iteration in run_yosys script for suites
sdamghan Jun 8, 2021
7730f44
[Odin]: Modify GTE, LTE, GT and LT circuits
sdamghan Jun 9, 2021
5c34331
[Infra]: Adding techmap full benchmarks to regreesion test
sdamghan Jun 9, 2021
ec69a82
[Odin]: fixing constant multiplier output sizes
sdamghan Jun 11, 2021
0a15961
[Odin]: fixing the subtraction conflict.
sdamghan Jun 11, 2021
43678d7
[Odin]: equalize the size of logical nodes' input ports
sdamghan Jun 11, 2021
aa55dfe
[Infra]: - Adding techmap full testing suite
sdamghan Jun 11, 2021
0ef7bd1
[Infra]: - Adding primitives modules (vtr_flow/primitives.v) as a lib…
sdamghan Jun 11, 2021
6662d2f
[Odin]: - Adding support for VTR primitives
sdamghan Jun 12, 2021
2c88008
[Odin]: - Adding techmap support for dual_port_ram
sdamghan Jun 12, 2021
f65ea40
[Infra]: reformatiing the regression_test/_BLIF
sdamghan Jun 12, 2021
fbcfaed
[Odin]: synchronize the clock port name in primitives, ODIN_II source…
sdamghan Jun 12, 2021
efc77de
[Odin]: - adding support for $dffsre sub-circuit
sdamghan Jun 18, 2021
2c3bbf7
[Odin]: - adding support for $mem (read write memory) in yosys blif
sdamghan Jun 19, 2021
e5f2ad4
[Odin]: - adding support for $pow sub-circuit
sdamghan Jun 20, 2021
cb22ed8
[Odin]: seperating case_equal functions from blif_elaborate
sdamghan Jun 20, 2021
11ee8e4
[Odin]: formating codes
sdamghan Jun 20, 2021
b58d1bb
[Odin]: adding support for constant exponentation
sdamghan Jun 20, 2021
55012c4
[Odin]: fixing the simulation bug for memory hard blocks
sdamghan Jun 20, 2021
e3ad182
[Odin]: fixing the BRAM clock signal simulation issue
sdamghan Jun 20, 2021
ea71351
[Infra]: regenerating expectation results
sdamghan Jun 20, 2021
a4ec289
[Odin]: - fixing dual write port bug for DPRAM and BRAM blocks
sdamghan Jun 20, 2021
0535ef3
[Odin]: - fixing undriven multiplier output pins
sdamghan Jun 20, 2021
552c0ae
[Odin]: - adding support for $sdffce sub-circuit
sdamghan Jun 20, 2021
dc8ae2e
[Odin]: - fixing over-freeing the constant multipication internal sig…
sdamghan Jun 21, 2021
9dada91
[Odin]: fixing throw exception for mismatching hard block port sizes …
sdamghan Jun 21, 2021
f929b05
[Odin]: - separating block memories and read only memories elaboration
sdamghan Jun 21, 2021
12d5511
[Infra]: Adding pmuxtree phase to yosys tcl script to resolve pmux su…
sdamghan Jun 21, 2021
94f5577
[Odin]: - adding support for mapping the read only memories and block…
sdamghan Jun 22, 2021
b99a0d4
[Infra]: regenerating new expectation results
sdamghan Jun 22, 2021
217c0ee
[Odin]: - adding threshold for LUTRAM inference
sdamghan Jun 23, 2021
034f9fa
[Odin]: - adding the Verilog Class to design
sdamghan Jun 23, 2021
96db6f6
[Infra]: - adding techmap large benchmark to regression suite for tec…
sdamghan Jun 23, 2021
a0a4053
[Odin]: Adding support for $sr sub-circuit
sdamghan Jun 23, 2021
42e3c2c
[Infra]: removing undriven signals from blif file using opt -undriven
sdamghan Jun 23, 2021
8a5585e
[Infra]: - fixing large benchmarks syntax errors
sdamghan Jun 24, 2021
c3fff2b
[Infra]: fixing task name in run_yosys and creating benchmark folder …
sdamghan Jun 24, 2021
3b4e861
[Infra]: - adding a techmap task for VTR benchmarks
sdamghan Jun 24, 2021
3661761
[Odin]: - fixing clock connectivity of arst flip flops (adff and adffe)
sdamghan Jun 24, 2021
4c132ce
[Odin]: refining the flip flop desings to optimize the final netlist
sdamghan Jun 25, 2021
3f96142
[Odin]: refining the spram and dpram inferrence
sdamghan Jun 25, 2021
ec432d5
[Infra]: organizing tasks with sub-folders in blif generation process…
sdamghan Jun 25, 2021
5cba585
[Infra]: changing large benchmarks to fix uninitialized reg errors
sdamghan Jun 25, 2021
9227282
[Infra]: considering relative path to BLIF directory in blif generati…
sdamghan Jun 25, 2021
b92063e
[Infra]: avoiding yosys to convert memory blocks to list of registers
sdamghan Jun 25, 2021
61e6069
[Infra]: - copying the single port RAM and Dual port RAM modules in v…
sdamghan Jun 25, 2021
793a021
[Infra]: adding new task for modified VTR benchmarks
sdamghan Jun 25, 2021
f325864
[Infra]: fixing hard block RAM errors for Modified VTR benchmark
sdamghan Jun 25, 2021
19c49d1
[Odin]: decoding output signal of dpram inferred from block memories …
sdamghan Jun 25, 2021
dc70717
[Odin]: Memory blocks and ROMs will be mapped only in one of the foll…
sdamghan Jun 26, 2021
96c6e58
[Odin]: fixing ROM->2R DPRAM clk connectivity
sdamghan Jun 26, 2021
9cf666c
[Odin]: - adding mem id to dpram, spram created from block memories
sdamghan Jun 26, 2021
16ac9e5
[Odin]: adding block memories 2r(spram) and 2rw(dpram) mapping
sdamghan Jun 26, 2021
63c5335
[Infra]: - removing simulation for large and modified VTR benchmark
sdamghan Jun 26, 2021
6922068
[Infra]: regenerating common expectation results
sdamghan Jun 26, 2021
956a984
[Odin]: removing spram from dpram list for optimization iteration
sdamghan Jun 26, 2021
555970a
[Odin]: splitting block memories in depth if needed in the case of im…
sdamghan Jun 26, 2021
dffd21a
[Infra]: - the depth variable in both_ram.v has changed due to the lo…
sdamghan Jun 26, 2021
7793f2a
[Infra]: regenerating new expectation results for micro benchmarks
sdamghan Jun 26, 2021
6a6078e
[Infra]: regenerating new expectation results for techmap operator be…
sdamghan Jun 26, 2021
35a0972
[Infra]: regenerating new expectation results for techmap full benchmark
sdamghan Jun 26, 2021
9d7715c
[Odin]: adding a new name convention for .cc files
sdamghan Jun 27, 2021
aa58963
[Infra]: - modifying arch files for tasks in techmap_suite
sdamghan Jun 28, 2021
5862f32
[Infra]: - modifying full and modifid vtr benchmark to include defaul…
sdamghan Jun 28, 2021
96a7ca3
[Infra]: adding missed yosys blif files for keywords tech suite
sdamghan Jun 28, 2021
fb7a870
[Infra]: adding techmap fpu/softlogic benchmarks to techmap
sdamghan Jun 28, 2021
8fed3ce
[Odin]: changing the variable name (signals) to avoid warnings in C++…
sdamghan Jun 28, 2021
6e17d21
[Infra]: adding fpu/softlogic blif files
sdamghan Jun 28, 2021
d577656
[Odin]: removing unused external declartion in memories.h
sdamghan Jun 28, 2021
1be70cb
[Infra]: removing blif file to avoid git lfs warnings
sdamghan Jun 28, 2021
6ca3649
[Odin]: - adding coarsen blif cleanup
sdamghan Jun 28, 2021
5248c8b
[Odin]: fix netlist vcc, gnd and pad names memory leak
sdamghan Jun 28, 2021
f768480
[Odin]: fixing memory leaks (pin->mapping)
sdamghan Jun 28, 2021
06a7904
[Odin]: fixing sanitizer leaks
sdamghan Jun 28, 2021
3760997
[infra]: regenerating new expectation results for techmap keywords be…
sdamghan Jun 28, 2021
54d6ccf
[Odin]: - moving bitset usage inside constant creation function
sdamghan Jun 29, 2021
128b771
[Odin]: fixing sanitizer error related to quotient pin mem leak
sdamghan Jun 29, 2021
dff33ab
[Odin]: - fixing mod pin leak error
sdamghan Jun 29, 2021
7312272
[Odin]: - fixing pad signals list memory leak in block memories
sdamghan Jun 29, 2021
5361934
[Infra]: regenerating new expectation results for techmap micro bench…
sdamghan Jun 29, 2021
cc65ad5
[Odin]: - optimization: reducing memory block address width based on …
sdamghan Jun 29, 2021
645459a
[Odin]: constant multipication port size reducation for useless pins
sdamghan Jun 29, 2021
0b224b6
[Infra]: adding full flag for yosys optimization
sdamghan Jun 30, 2021
c30a86a
[Odin]: - adding constant shift implementation to partial mapping to …
sdamghan Jun 30, 2021
e0f3841
[Infra]: regenerating new expectation results
sdamghan Jun 30, 2021
53af6f2
[Odin]: formatting the code style
sdamghan Jun 30, 2021
c5b7e2d
[Odin]: fixing multiliers memory leak while Odin runs with verilog files
sdamghan Jun 30, 2021
0e19fa6
[Odin]: resolving memory leaks and segfault resulted by BUF_NODE
sdamghan Jul 1, 2021
7761e66
[Odin]: Adding cin pin to add and sub sub-circuits when adder hard bl…
sdamghan Jul 1, 2021
5eed51d
[Odin]: - fixing subtraction input pins leak while using arch with ha…
sdamghan Jul 1, 2021
d6eeee3
[Infra]: - regenerating _BLIF/syntax new expectation results using sa…
sdamghan Jul 1, 2021
e9b03b1
[Odin]: fixing $reduce_and sub-circuit inference
sdamghan Jul 1, 2021
bf570bd
[Infra]: - regenerating _BLIF/full new expectation results using sani…
sdamghan Jul 1, 2021
e84d848
[Odin]: fixing mem leak for related_ast_node for ram blocks
sdamghan Jul 2, 2021
11f2816
[Infra]: - adding default arg for modified VTR benchmarks
sdamghan Jul 2, 2021
145e544
[Infra]: removing extra verilog files for techmap regression tests
sdamghan Jul 3, 2021
8a0005c
[Infra]: fixing adding duplicate blif files generated run_yosys.sh
sdamghan Jul 3, 2021
1e7fffe
[Odin]: fixing segfault for traversing backward if a pin is undriven
sdamghan Jul 3, 2021
140d40e
[Odin]: fixing segfault resulteb by freeing a buf node if the buf nod…
sdamghan Jul 3, 2021
1400f1a
[Odin]: fixing blif_writer pointer mem leak
sdamghan Jul 3, 2021
ea15e4d
[Odin]: fixing overfreeing pad_string in the case of unconnected inputs
sdamghan Jul 3, 2021
8eedcac
[Odin]: padding nets without drivers with PAD instead of GND to avoid…
sdamghan Jul 3, 2021
e538b05
[Odin]: avoiding reordering vcc and gnd net pins (partial map travers…
sdamghan Jul 3, 2021
2c18f8e
[Infra]: updating lightsuite expectation results with new output stat…
sdamghan Jul 3, 2021
83f4cee
[Infra]: updating heavy_suite expectation results with new output sta…
sdamghan Jul 4, 2021
c0db806
[Infra]: regenerating techmap_suite expectation results using sanitizer
sdamghan Jul 4, 2021
244877b
[Odin]: formating code
sdamghan Jul 4, 2021
c245fa5
[Odin]: avoiding segfault for net visualizer (null pointer for remove…
sdamghan Jul 4, 2021
1e6d5f7
[Infra]: - building yosys in odin_reg_techmap CI test
sdamghan Jul 4, 2021
50b1e74
[Infra]: - generating yosys BLIF file when techmap suite is called
sdamghan Jul 4, 2021
7d842ec
[Infra]: - generating yosys blif IF the benchmarks blif do not exist
sdamghan Jul 5, 2021
f98eae0
[Infra]: - improving run_yosys.sh help function
sdamghan Jul 5, 2021
5066a9c
[Infra]: generating yosys blif files for run_reg_test/odin_reg_techma…
sdamghan Jul 5, 2021
9cf01e8
[Vtrutil]: adding getline with comment igorance (compatible with both…
sdamghan Jul 6, 2021
d6fa091
[Odin]: adding getbline to read BLIFs according to line styles (getli…
sdamghan Jul 6, 2021
80f2865
[CI]: adding odin_tech_basic and odin_tech_strong
sdamghan Jul 6, 2021
7a3663a
[Odin]: - fixing netlist identifier mem leak if blif file is empty
sdamghan Jul 6, 2021
24cb5be
[Odin]: - fixing clang non-trival type passing error
sdamghan Jul 6, 2021
6b5320b
[Infra]: - regenerating _BLIF/full expectation results
sdamghan Jul 7, 2021
6c66d1d
[Infra]: command arg to run a single benchmark in run_yosys script
sdamghan Jul 8, 2021
ae3a9c8
[Odin]: cleaning up the old soft mult node after splitting
sdamghan Jul 8, 2021
91e2a40
[Odin]: driving undriven nets with ZEROs
sdamghan Jul 12, 2021
a056e42
[Flow]: updating mult_consts golden results
sdamghan Jul 12, 2021
deca3dc
[Flow]: fixing undriven hard block clk pin in koios/attention_layer
sdamghan Jul 12, 2021
6006d32
[Infra]: Adding odin_tech_strong to kokoro
sdamghan Jul 13, 2021
30ef96c
[Odin]: pruning extra pad pins from yosys generated subtraction node
sdamghan Jul 18, 2021
59c6a17
[Odin]: fix create constant signal list indexing
sdamghan Jul 18, 2021
b8e0478
[Odin]: fixing asynchrounous dffs connectivities
sdamghan Jul 19, 2021
5325762
[Odin]: - spliting logical nodes in single bit logical nodes
sdamghan Jul 19, 2021
d959a64
[Odin]: - removing unused constant shift operand pins
sdamghan Jul 19, 2021
d57be5f
[Odin]: fix equalize subtraction ports bug
sdamghan Jul 19, 2021
a58ff8e
[Infra]: - removing fine grain optimiztion in synth tcl script
sdamghan Jul 19, 2021
232e9c4
[Odin]: fixing simulation mismatch
sdamghan Jul 19, 2021
6f9dd2f
[Odin]: - checking addr port equality for BRAMs
sdamghan Jul 19, 2021
3762d8f
[Odin]: - extra logiccal node outputs are driven with PAD node
sdamghan Jul 20, 2021
8152a30
[Odin]: - adding pure const binary operation
sdamghan Jul 21, 2021
1d5b12d
[Odin]: perform logical node optimization
sdamghan Jul 21, 2021
6504348
[Odin]: - removing OR chain for memories enables
sdamghan Jul 21, 2021
6c49b68
[Odin]: regenerate techmap_lightsuite expectation results
sdamghan Jul 21, 2021
dfd6bf6
[Odin]: removing checking a stage before mem blocks for matching ports
sdamghan Jul 21, 2021
f5cbd90
[Odin]: separating one-hot mux_2 with mux_2 with single selector (SMU…
sdamghan Jul 21, 2021
72c4c00
[Odin]: reformat ff structures with smux_2
sdamghan Jul 21, 2021
d4aa7c9
[Odin]: improve various ff inference and tide-up Flipflop .cc file
sdamghan Jul 21, 2021
8a267ba
[Odin]: regenerate techmap_lightsuite expectation results
sdamghan Jul 21, 2021
1c051ae
[Odin]: adding nr/nrnw support using muxed read/write ports
sdamghan Jul 24, 2021
4b19e72
[Odin]: improving area of shift circuits by instantiating mux with si…
sdamghan Jul 24, 2021
e7b084c
[Odin]: Update techmap_light suite expectation results
sdamghan Jul 24, 2021
25a59cb
[Odin]: updatnge expectation results
sdamghan Jul 24, 2021
ee4be90
[Odin]: - refomart the input section for odin xml config file
sdamghan Jul 25, 2021
b8ddcfc
[Infra]: adding vtr task for modified vtr benchmarks running by yosys…
sdamghan Jul 25, 2021
cf0d42e
[Odin]: - resolve asynchronous dff to formal one by Yosys
sdamghan Jul 27, 2021
741f613
[Odin]: adding Odin techlib for BRAM and ROM
sdamghan Jul 28, 2021
91b6cf1
[Odin]: adding ymem sub-circuit
sdamghan Jul 28, 2021
62747fb
[Odin]: - adding -o option to run_yosys
sdamghan Jul 28, 2021
a7f63bf
[Odin]: fix segfault for large npbMUXes
sdamghan Jul 29, 2021
a3ddaf9
[Odin]: fix clock node counting during blif elaboration
sdamghan Jul 29, 2021
3cc3ab7
[Odin]: regenerating techmap expectation results
sdamghan Jul 29, 2021
610d8e1
[Odin]: adding fflegalize option to make all FF rising edge
sdamghan Jul 30, 2021
a7bb75e
[Odin]: - adding storing yosys log option to run_yosys
sdamghan Aug 2, 2021
1a5cad0
[Odin]: adding review comments
sdamghan Aug 2, 2021
4806a2e
[Odin]: - adding file-scope comments
sdamghan Aug 3, 2021
4d53169
[Odin]: reformat instantiation of subtraction with borrow signals
sdamghan Aug 3, 2021
028a127
[Odin]: regenerating techmap expectation results
sdamghan Aug 3, 2021
882ae3f
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
sdamghan Aug 3, 2021
78f3cbb
[Odin]: make format
sdamghan Aug 3, 2021
3398af4
[Odin]: removing extra spram/dpram module definitions in benchmarks hdl
sdamghan Aug 5, 2021
535ae8f
[Odin]: - fixing SPRAM/DPRAM verificatory bug
sdamghan Aug 6, 2021
ca76b4a
[Odin]: integrate Yosys elaborator inside Odin-II
sdamghan Aug 6, 2021
934a40b
[Odin]: - fix run_yosys and verify odin bug
sdamghan Aug 8, 2021
1f1d473
[Odin]: reformat yosys+odin task files
sdamghan Aug 8, 2021
6045eba
[Odin]: fix custom SP/DP RAM names read by BLIFReader
sdamghan Aug 9, 2021
eca67a1
[Odin]: move _VERILOG to verilog/yosys_compatible_verilogs
sdamghan Aug 9, 2021
23ee3af
[Odin]: refactor techmap_light suite, FIR and full benchmarks for yos…
sdamghan Aug 9, 2021
d302dcc
[Odin]: - refactoring techmap_heavysuite for yosys+odin
sdamghan Aug 10, 2021
b27c8ae
[Odin]: - update techmap expectations
sjkelly Jul 31, 2021
6f00613
[Odin]: - fix get_root_directory bug
sdamghan Aug 11, 2021
425a47e
[Infra]: - create a new GitHub action job for vtr_reg_Yosys+Odin and …
sdamghan Aug 11, 2021
d36ddc2
[Infra]: adding yosys as a submodule to VTR repo
sdamghan Aug 11, 2021
d8b6a0d
[Odin]: fix swept pins for sdffce
sdamghan Aug 12, 2021
3f005ce
[Infra]: adding a new Kokoro test for Yosys+Odin VTR reg test
sdamghan Aug 12, 2021
2a2f74c
[Infra]: - remove yosys submodule
sdamghan Aug 12, 2021
aa17192
Squashed 'yosys/' content from commit b96eb888c
sdamghan Aug 12, 2021
c8c3cfc
Merge commit 'aa17192b7b70640a19f9aa3482f9dcdab1b52ae1' as 'yosys'
sdamghan Aug 12, 2021
bcfeda4
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
sdamghan Aug 12, 2021
6ec6ca8
[Infra]: update Koios benchmarks with yosys-compatible version
sdamghan Aug 12, 2021
36ef369
[Infra]: fix VTR and fpu/softlogic benchmarks errors
sdamghan Aug 13, 2021
1bda319
[Odin]: - fix VTR, Koios and fpu task files for Odin verification script
sdamghan Aug 13, 2021
0f8687a
[Odin]: - set Yosys executable path to the VTR/yosys
sdamghan Aug 13, 2021
9944bcd
[Infra]: add yosys to EXTERNAL libs
sdamghan Aug 13, 2021
5acc967
[Infra]: - add CMakeList.txt to libyosys
sdamghan Aug 14, 2021
926c927
[Infra]: add "-DODIN_USE_YOSYS=ON" to config files of GitHub action a…
sdamghan Aug 15, 2021
6954a87
[Odin]: - call Yosys in a fork process to handle Yosys failure
sdamghan Aug 16, 2021
cb9bb43
[Odin]: - add Yosys+Odin-II common benchmarks with Odin-II benchmarks
sdamghan Aug 16, 2021
b5e041d
[Odin]: - merge Yosys+Odin-II operator benchmarks with Odin-II operar…
sdamghan Aug 16, 2021
eada456
[Odin]: - merge Yosys+Odin-II FIR benchmarks with Odin-II FIR benchmarks
sdamghan Aug 16, 2021
ec882bf
[Odin]: - merge Yosys+Odin-II syntax benchmarks with Odin-II syntax b…
sdamghan Aug 16, 2021
0119d26
[Odin]: - merge Yosys+Odin-II micro benchmarks with Odin-II micro ben…
sdamghan Aug 16, 2021
a8d3c29
[Odin]: - merge Yosys+Odin-II full benchmarks with Odin-II full bench…
sdamghan Aug 16, 2021
6128b36
[Odin]: - merge Yosys+Odin-II large benchmarks with Odin-II large ben…
sdamghan Aug 16, 2021
dfff7ca
[Odin]: - merge Yosys+Odin-II preprocessor and c_functions benchmarks…
sdamghan Aug 16, 2021
46cc609
[Odin]: merge Odin-II keyword suite with Yosys+Odin-II
sdamghan Aug 16, 2021
5801a1c
[Odin]: - mkDelayWorker syntax error in Odin-II
sdamghan Aug 16, 2021
ba34a7a
[Odin]: fix verify_script bug for simulation vector posfix detection
sdamghan Aug 17, 2021
9c86160
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
sdamghan Aug 17, 2021
d779c50
[Odin]: - regenerate expectation results of arch_sweep benchmarks
sdamghan Aug 17, 2021
34c3c69
[Odin]: - add a review comment for unused_node cutoff in Odin-II netl…
sdamghan Aug 19, 2021
35acb0c
[Infra]: invert yosys+odin changes to vtr_flow/benchmarks
sdamghan Aug 19, 2021
40f0d37
[Infra]: make VTR benchmarks compatible with Yosys+Odin
sdamghan Aug 19, 2021
3e86cda
[Infra]: - regenerate vtr_reg_yosys_odin golden results
sdamghan Aug 19, 2021
4cb3b2f
[Odin]: - fix invalid mux decoder indexing
sdamghan Aug 19, 2021
abbd702
[Infra]: update vtr_reg_nightly_test3 and vtr_reg_nightly_test1/power…
sdamghan Aug 20, 2021
0bef7ed
[Odin]: - fix Odin-II's techmap flow codebase format
sdamghan Aug 21, 2021
34b994f
[Infra]: generate vtr_reg_yosys_odin golden results
sdamghan Aug 22, 2021
446f5be
[Odin]: add -S/--tcl option to run Yosys in Odin-II
sdamghan Aug 22, 2021
2d6e53a
[Odin]: - fix mkDelayWorker32B and mcml dpram sizes bug in Odin/VTR b…
sdamghan Aug 23, 2021
6bff4a4
Merge branch 'master' into yosys+odin
vaughnbetz Aug 31, 2021
3e581f7
Updated mcml output count for golden_results of vtr_reg_qor_chain_pre…
vaughnbetz Sep 2, 2021
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61 changes: 61 additions & 0 deletions .github/kokoro/continuous/odin_tech_strong.cfg
Original file line number Diff line number Diff line change
@@ -0,0 +1,61 @@
# Format: //devtools/kokoro/config/proto/build.proto
# Odin_tech_strong test checks the Odin-II technology mapping for
# Yosys+Odin-II over Odin-II techmap_heavysuite (excluding ABC and VPR)

build_file: "vtr-verilog-to-routing/.github/kokoro/run-vtr.sh"

# 12 hours
timeout_mins: 720

action {
define_artifacts {
# File types
regex: "**/*.out"
regex: "**/vpr_stdout.log"
regex: "**/parse_results.txt"
regex: "**/qor_results.txt"
regex: "**/pack.log"
regex: "**/place.log"
regex: "**/route.log"
regex: "**/*_qor.csv"
strip_prefix: "github/vtr-verilog-to-routing/"
}
}

env_vars {
key: "KOKORO_TYPE"
value: "continuous"
}

env_vars {
key: "KOKORO_DIR"
value: "vtr-verilog-to-routing"
}

env_vars {
key: "VTR_DIR"
value: "vtr-verilog-to-routing"
}

#Use default build configuration
env_vars {
key: "VTR_CMAKE_PARAMS"
value: "-DODIN_USE_YOSYS=ON"
}

env_vars {
key: "VTR_TEST"
value: "odin_tech_strong"
}

#Options for run_reg_test.py
# -show_failures: show tool failures in main log output
env_vars {
key: "VTR_TEST_OPTIONS"
value: "-show_failures"
}

env_vars {
key: "NUM_CORES"
value: "3"
}
69 changes: 69 additions & 0 deletions .github/kokoro/continuous/yosys_odin_test.cfg
Original file line number Diff line number Diff line change
@@ -0,0 +1,69 @@
# Format: //devtools/kokoro/config/proto/build.proto
# vtr_reg_yosys_odin test runs the VTR benchmarks through
# the entire VTR with Yosys+Odin-II as the first CAD tool

build_file: "vtr-verilog-to-routing/.github/kokoro/run-vtr.sh"

# 72 hours
timeout_mins: 4320

action {
define_artifacts {
# File types
regex: "**/*.out"
regex: "**/vpr_stdout.log"
regex: "**/parse_results.txt"
regex: "**/qor_results.txt"
regex: "**/pack.log"
regex: "**/place.log"
regex: "**/route.log"
regex: "**/*_qor.csv"
regex: "**/*.out.gz"
regex: "**/vpr_stdout.log.gz"
regex: "**/parse_results.txt.gz"
regex: "**/qor_results.txt.gz"
regex: "**/pack.log.gz"
regex: "**/place.log.gz"
regex: "**/route.log.gz"
regex: "**/*_qor.csv.gz"
strip_prefix: "github/vtr-verilog-to-routing/"
}
}

env_vars {
key: "KOKORO_TYPE"
value: "continuous"
}

env_vars {
key: "KOKORO_DIR"
value: "vtr-verilog-to-routing"
}

env_vars {
key: "VTR_DIR"
value: "vtr-verilog-to-routing"
}

#Use default build configuration
env_vars {
key: "VTR_CMAKE_PARAMS"
value: "-DODIN_USE_YOSYS=ON"
}

env_vars {
key: "VTR_TEST"
value: "vtr_reg_yosys_odin"
}

#Options for run_reg_test.py
# -show_failures: show tool failures in main log output
env_vars {
key: "VTR_TEST_OPTIONS"
value: "-show_failures"
}

env_vars {
key: "NUM_CORES"
value: "8"
}
61 changes: 61 additions & 0 deletions .github/kokoro/presubmit/odin_tech_strong.cfg
Original file line number Diff line number Diff line change
@@ -0,0 +1,61 @@
# Format: //devtools/kokoro/config/proto/build.proto
# Odin_tech_strong test checks the Odin-II technology mapping for
# Yosys+Odin-II over Odin-II techmap_heavysuite (excluding ABC and VPR)

build_file: "vtr-verilog-to-routing/.github/kokoro/run-vtr.sh"

# 12 hours
timeout_mins: 720

action {
define_artifacts {
# File types
regex: "**/*.out"
regex: "**/vpr_stdout.log"
regex: "**/parse_results.txt"
regex: "**/qor_results.txt"
regex: "**/pack.log"
regex: "**/place.log"
regex: "**/route.log"
regex: "**/*_qor.csv"
strip_prefix: "github/vtr-verilog-to-routing/"
}
}

env_vars {
key: "KOKORO_TYPE"
value: "presubmit"
}

env_vars {
key: "KOKORO_DIR"
value: "vtr-verilog-to-routing"
}

env_vars {
key: "VTR_DIR"
value: "vtr-verilog-to-routing"
}

#Use default build configuration
env_vars {
key: "VTR_CMAKE_PARAMS"
value: "-DODIN_USE_YOSYS=ON"
}

env_vars {
key: "VTR_TEST"
value: "odin_tech_strong"
}

#Options for run_reg_test.py
# -show_failures: show tool failures in main log output
env_vars {
key: "VTR_TEST_OPTIONS"
value: "-show_failures"
}

env_vars {
key: "NUM_CORES"
value: "3"
}
69 changes: 69 additions & 0 deletions .github/kokoro/presubmit/yosys_odin_test.cfg
Original file line number Diff line number Diff line change
@@ -0,0 +1,69 @@
# Format: //devtools/kokoro/config/proto/build.proto
# vtr_reg_yosys_odin test runs the VTR benchmarks through
# the entire VTR with Yosys+Odin-II as the first CAD tool

build_file: "vtr-verilog-to-routing/.github/kokoro/run-vtr.sh"

# 72 hours
timeout_mins: 4320

action {
define_artifacts {
# File types
regex: "**/*.out"
regex: "**/vpr_stdout.log"
regex: "**/parse_results.txt"
regex: "**/qor_results.txt"
regex: "**/pack.log"
regex: "**/place.log"
regex: "**/route.log"
regex: "**/*_qor.csv"
regex: "**/*.out.gz"
regex: "**/vpr_stdout.log.gz"
regex: "**/parse_results.txt.gz"
regex: "**/qor_results.txt.gz"
regex: "**/pack.log.gz"
regex: "**/place.log.gz"
regex: "**/route.log.gz"
regex: "**/*_qor.csv.gz"
strip_prefix: "github/vtr-verilog-to-routing/"
}
}

env_vars {
key: "KOKORO_TYPE"
value: "presubmit"
}

env_vars {
key: "KOKORO_DIR"
value: "vtr-verilog-to-routing"
}

env_vars {
key: "VTR_DIR"
value: "vtr-verilog-to-routing"
}

#Use default build configuration
env_vars {
key: "VTR_CMAKE_PARAMS"
value: "-DODIN_USE_YOSYS=ON"
}

env_vars {
key: "VTR_TEST"
value: "vtr_reg_yosys_odin"
}

#Options for run_reg_test.py
# -show_failures: show tool failures in main log output
env_vars {
key: "VTR_TEST_OPTIONS"
value: "-show_failures"
}

env_vars {
key: "NUM_CORES"
value: "8"
}
4 changes: 3 additions & 1 deletion .github/kokoro/run-vtr.sh
Original file line number Diff line number Diff line change
Expand Up @@ -10,13 +10,15 @@ ls -l
cd github
ls -l
cd vtr-verilog-to-routing
export VTR_DIR=$( pwd )
source $SCRIPT_DIR/steps/hostsetup.sh
source $SCRIPT_DIR/steps/hostinfo.sh

# Output git information
source $SCRIPT_DIR/steps/git.sh

if [ $VTR_TEST == "vtr_reg_strong" ] || [ $VTR_TEST == "odin_reg_strong" ]; then
if [ $VTR_TEST == "vtr_reg_strong" ] || [ $VTR_TEST == "odin_reg_strong" ] \
|| [ $VTR_TEST == "odin_tech_strong" ] || [ $VTR_TEST == "vtr_reg_yosys_odin" ]; then
source $SCRIPT_DIR/steps/vtr-min-setup.sh
else
source $SCRIPT_DIR/steps/vtr-full-setup.sh
Expand Down
11 changes: 11 additions & 0 deletions .github/kokoro/steps/hostsetup.sh
Original file line number Diff line number Diff line change
Expand Up @@ -56,6 +56,17 @@ sudo apt-get install -y \
python3-yaml \
qt5-default \
virtualenv \
clang \
libreadline-dev \
gawk \
tcl-dev \
libffi-dev \
xdot \
pkg-config \
libboost-system-dev \
libboost-python-dev \
libboost-filesystem-dev \
zlib1g-dev \
#Don't include libtbb-dev since it may increase memory usage
#libtbb-dev \

Expand Down
3 changes: 3 additions & 0 deletions .github/scripts/install_dependencies.sh
Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,9 @@ sudo apt install -y \
libx11-dev \
libxft-dev \
libxml++2.6-dev \
libreadline-dev \
tcl-dev \
libffi-dev \
perl \
texinfo \
time \
Expand Down
32 changes: 31 additions & 1 deletion .github/workflows/test.yml
Original file line number Diff line number Diff line change
Expand Up @@ -167,7 +167,7 @@ jobs:


ODINII:
name: 'ODIN-II Basic Tests'
name: 'ODIN-II Basic Test'
runs-on: ubuntu-18.04
steps:

Expand All @@ -186,6 +186,35 @@ jobs:
./run_reg_test.py odin_reg_basic -show_failures -j2


YOSYSODINII:
runs-on: ubuntu-18.04
strategy:
fail-fast: false
matrix:
include: [
{
name: 'Yosys+ODIN-II Basic',
suite: 'odin_tech_basic'
}
]
name: '${{ matrix.name }}'
steps:

- uses: actions/setup-python@v2
with:
python-version: 3.6
- uses: actions/checkout@v2
- run: ./.github/scripts/install_dependencies.sh

- name: Test
env:
CMAKE_PARAMS: '-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=on -DVTR_IPO_BUILD=off -DWITH_BLIFEXPLORER=on -DODIN_USE_YOSYS=ON'
BUILD_TYPE: debug
run: |
./.github/scripts/build.sh
./run_reg_test.py ${{ matrix.suite }} -show_failures -j2


Compatibility:
runs-on: ubuntu-18.04
strategy:
Expand Down Expand Up @@ -227,6 +256,7 @@ jobs:
- Regression
- Sanitized
- ODINII
- YOSYSODINII
- Compatibility
runs-on: ubuntu-18.04
steps:
Expand Down
3 changes: 3 additions & 0 deletions CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -51,6 +51,9 @@ option(ODIN_COVERAGE "Enable building odin with coverage flags" OFF)
option(ODIN_TIDY "Enable building odin with clang tidy" OFF)
option(ODIN_SANITIZE "Enable building odin with sanitize flags" OFF)

# Allow the user to enable building Yosys
option(ODIN_USE_YOSYS "Enable building Yosys" OFF)

set(VTR_VERSION_MAJOR 8)
set(VTR_VERSION_MINOR 1)
set(VTR_VERSION_PATCH 0)
Expand Down
2 changes: 2 additions & 0 deletions ODIN_II/.gitignore
Original file line number Diff line number Diff line change
@@ -1,6 +1,8 @@
regression_test/run*
regression_test/benchmark/_BLIF
regression_test/latest

/yosys
/temp
/*.v
/*.blif
Expand Down
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