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8841e5a
[VPR] Add comments about API in rr_graph_builder
tangxifan Jul 18, 2021
60e209a
[VPR] Added a new API find_grid_nodes_at_all_sides() and deploy to cl…
tangxifan Jul 19, 2021
1d63c47
[VPR] Remove find_sink_nodes() API because it is a subset of API find…
tangxifan Jul 19, 2021
b0e37cf
[VPR] Now t_rr_edge_set data structure adapts RRNodeId; Fully shadowe…
tangxifan Jul 19, 2021
5581815
[VPR] Remove out-of-date functions related to rr_node_indices
tangxifan Jul 19, 2021
aa32abd
[VPR] Code format fix
tangxifan Jul 19, 2021
9074d45
[VPR] Fix small typo in RRGraphBuilder comments
tangxifan Jul 19, 2021
29383fb
[VPR] Remove the use of scratchpad as a variable across functions; Ad…
tangxifan Jul 19, 2021
87112cc
[VPR] Remove t_opin_connections_scratchpad; Use natural vector defini…
tangxifan Jul 20, 2021
4452b2f
[VPR] Try to fix the error seen in sanity checks through using STL
tangxifan Jul 20, 2021
61670b4
[VPR] See RAM explosion on CI when sanity check is enabled. Try to re…
tangxifan Jul 20, 2021
a72a771
[VPR] Reserve memory in RRSpatialLookUp to avoid memory fragement
tangxifan Jul 21, 2021
4d40785
[VPR] Remove the use of scratchpad and vectors in timing placer lookup
tangxifan Jul 21, 2021
2023e27
[VPR] Code format fix
tangxifan Jul 21, 2021
9295ac8
[VPR] Add reserve_nodes() API to RRSpatialLookup for memory efficiency
tangxifan Jul 21, 2021
5f4247a
[VPR] Remove the use of SIDES[0] when adding a node to RRSpatialLookup
tangxifan Jul 21, 2021
5c9d3b7
[VPR] Bug fix due to wrongly reserve nodes
tangxifan Jul 21, 2021
d7a9ea4
[VPR] Fixed type error in the heap of connection router
tangxifan Jul 22, 2021
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2 changes: 1 addition & 1 deletion utils/route_diag/src/main.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -170,7 +170,7 @@ static void profile_source(int source_rr_node,
for (int sink_ptc : best_sink_ptcs) {
VTR_ASSERT(sink_ptc != OPEN);

int sink_rr_node = get_rr_node_index(device_ctx.rr_node_indices, sink_x, sink_y, SINK, sink_ptc);
int sink_rr_node = size_t(device_ctx.rr_graph.node_lookup().find_node(sink_x, sink_y, SINK, sink_ptc));

if (directconnect_exists(source_rr_node, sink_rr_node)) {
//Skip if we shouldn't measure direct connects and a direct connect exists
Expand Down
2 changes: 2 additions & 0 deletions vpr/src/device/rr_graph_builder.h
Original file line number Diff line number Diff line change
Expand Up @@ -38,6 +38,8 @@ class RRGraphBuilder {
/* Return a writable object for update the fast look-up of rr_node */
RRSpatialLookup& node_lookup();
/* Add an existing rr_node in the node storage to the node look-up
* The node will be added to the lookup for every side it is on (for OPINs and IPINs)
* and for every (x,y) location at which it exists (for wires that span more than one (x,y)).
* This function requires a valid node which has already been allocated in the node storage, with
* - a valid node id
* - valid geometry information: xlow/ylow/xhigh/yhigh
Expand Down
56 changes: 51 additions & 5 deletions vpr/src/device/rr_spatial_lookup.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -122,6 +122,15 @@ std::vector<RRNodeId> RRSpatialLookup::find_nodes(int x,
return nodes;
}

/* Reserve space to avoid memory fragmentation */
size_t num_nodes = 0;
for (const auto& node : rr_node_indices_[type][node_x][node_y][side]) {
if (RRNodeId(node)) {
num_nodes++;
}
}

nodes.reserve(num_nodes);
for (const auto& node : rr_node_indices_[type][node_x][node_y][side]) {
if (RRNodeId(node)) {
nodes.push_back(RRNodeId(node));
Expand All @@ -142,11 +151,6 @@ std::vector<RRNodeId> RRSpatialLookup::find_channel_nodes(int x,
return find_nodes(x, y, type);
}

std::vector<RRNodeId> RRSpatialLookup::find_sink_nodes(int x,
int y) const {
return find_nodes(x, y, SINK);
}

std::vector<RRNodeId> RRSpatialLookup::find_nodes_at_all_sides(int x,
int y,
t_rr_type rr_type,
Expand All @@ -155,13 +159,15 @@ std::vector<RRNodeId> RRSpatialLookup::find_nodes_at_all_sides(int x,

/* TODO: Consider to access the raw data like find_node() rather than calling find_node() many times, which hurts runtime */
if (rr_type == IPIN || rr_type == OPIN) {
indices.reserve(NUM_SIDES);
//For pins we need to look at all the sides of the current grid tile
for (e_side side : SIDES) {
RRNodeId rr_node_index = find_node(x, y, rr_type, ptc, side);
if (rr_node_index) {
indices.push_back(rr_node_index);
}
}
indices.shrink_to_fit();
} else {
//Sides do not effect non-pins so there should only be one per ptc
RRNodeId rr_node_index = find_node(x, y, rr_type, ptc);
Expand All @@ -173,6 +179,46 @@ std::vector<RRNodeId> RRSpatialLookup::find_nodes_at_all_sides(int x,
return indices;
}

std::vector<RRNodeId> RRSpatialLookup::find_grid_nodes_at_all_sides(int x,
int y,
t_rr_type rr_type) const {
VTR_ASSERT(rr_type == SOURCE || rr_type == OPIN || rr_type == IPIN || rr_type == SINK);
if (rr_type == SOURCE || rr_type == SINK) {
return find_nodes(x, y, rr_type);
}

std::vector<RRNodeId> nodes;
/* Reserve space to avoid memory fragmentation */
size_t num_nodes = 0;
for (e_side node_side : SIDES) {
num_nodes += find_nodes(x, y, rr_type, node_side).size();
}

nodes.reserve(num_nodes);
for (e_side node_side : SIDES) {
std::vector<RRNodeId> temp_nodes = find_nodes(x, y, rr_type, node_side);
nodes.insert(nodes.end(), temp_nodes.begin(), temp_nodes.end());
}
return nodes;
}

void RRSpatialLookup::reserve_nodes(int x,
int y,
t_rr_type type,
int num_nodes,
e_side side) {
VTR_ASSERT_SAFE(3 == rr_node_indices_[type].ndims());

/* For non-IPIN/OPIN nodes, the side should always be the TOP side which follows the convention in find_node() API! */
if (type != IPIN && type != OPIN) {
VTR_ASSERT(side == SIDES[0]);
}

resize_nodes(x, y, type, side);

rr_node_indices_[type][x][y][side].reserve(num_nodes);
}

void RRSpatialLookup::add_node(RRNodeId node,
int x,
int y,
Expand Down
31 changes: 18 additions & 13 deletions vpr/src/device/rr_spatial_lookup.h
Original file line number Diff line number Diff line change
Expand Up @@ -81,30 +81,35 @@ class RRSpatialLookup {
int y,
t_rr_type type) const;

/**
* Returns the indices of the specified routing resource nodes,
* representing virtual sinks.
* - (x, y) are the coordinate of the sink nodes within the FPGA
*
* Note:
* - Return an empty list if there are no sinks at the given (x, y) location
* - The node list returned only contains valid ids
*/
std::vector<RRNodeId> find_sink_nodes(int x,
int y) const;

/**
* Like find_node() but returns all matching nodes on all the sides.
* This is particularly useful for getting all instances
* of a specific IPIN/OPIN at a specific gird tile (x,y) location.
* of a specific IPIN/OPIN at a specific grid tile (x,y) location.
*/
std::vector<RRNodeId> find_nodes_at_all_sides(int x,
int y,
t_rr_type rr_type,
int ptc) const;

/**
* Returns all matching nodes on all the sides at a specific grid tile (x,y) location.
* As this is applicable to grid pins, the type of nodes are limited to SOURCE/SINK/IPIN/OPIN
*/
std::vector<RRNodeId> find_grid_nodes_at_all_sides(int x,
int y,
t_rr_type rr_type) const;

/* -- Mutators -- */
public:
/**
* Reserve the memory for a list of nodes at (x, y) location with given type and side
*/
void reserve_nodes(int x,
int y,
t_rr_type type,
int num_nodes,
e_side side = SIDES[0]);

/**
* Register a node in the fast look-up
* - You must have a valid node id to register the node in the lookup
Expand Down
27 changes: 11 additions & 16 deletions vpr/src/place/timing_place_lookup.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -142,8 +142,7 @@ static bool find_direct_connect_sample_locations(const t_direct_inf* direct,
int to_pin,
int to_pin_class,
int* src_rr,
int* sink_rr,
std::vector<RRNodeId>* scratch);
int* sink_rr);

static bool verify_delta_delays(const vtr::Matrix<float>& delta_delays);

Expand Down Expand Up @@ -955,8 +954,7 @@ static bool find_direct_connect_sample_locations(const t_direct_inf* direct,
int to_pin,
int to_pin_class,
int* src_rr,
int* sink_rr,
std::vector<RRNodeId>* scratch) {
int* sink_rr) {
VTR_ASSERT(from_type != nullptr);
VTR_ASSERT(to_type != nullptr);

Expand All @@ -983,8 +981,7 @@ static bool find_direct_connect_sample_locations(const t_direct_inf* direct,
RRNodeId from_pin_rr = node_lookup.find_node(from_x, from_y, OPIN, from_pin, direct->from_side);
from_pin_found = (from_pin_rr != RRNodeId::INVALID());
} else {
(*scratch) = node_lookup.find_nodes_at_all_sides(from_x, from_y, OPIN, from_pin);
from_pin_found = !(*scratch).empty();
from_pin_found = !(node_lookup.find_nodes_at_all_sides(from_x, from_y, OPIN, from_pin).empty());
}
if (!from_pin_found) continue;

Expand All @@ -1000,8 +997,7 @@ static bool find_direct_connect_sample_locations(const t_direct_inf* direct,
RRNodeId to_pin_rr = node_lookup.find_node(to_x, to_y, IPIN, to_pin, direct->to_side);
to_pin_found = (to_pin_rr != RRNodeId::INVALID());
} else {
(*scratch) = node_lookup.find_nodes_at_all_sides(to_x, to_y, IPIN, to_pin);
to_pin_found = !(*scratch).empty();
to_pin_found = !(node_lookup.find_nodes_at_all_sides(to_x, to_y, IPIN, to_pin).empty());
}
if (!to_pin_found) continue;

Expand Down Expand Up @@ -1038,15 +1034,15 @@ static bool find_direct_connect_sample_locations(const t_direct_inf* direct,
//

{
(*scratch) = node_lookup.find_nodes_at_all_sides(from_x, from_y, SOURCE, from_pin_class);
VTR_ASSERT((*scratch).size() > 0);
*src_rr = size_t((*scratch)[0]);
RRNodeId src_rr_candidate = node_lookup.find_node(from_x, from_y, SOURCE, from_pin_class);
VTR_ASSERT(src_rr_candidate);
*src_rr = size_t(src_rr_candidate);
}

{
(*scratch) = node_lookup.find_nodes_at_all_sides(to_x, to_y, SINK, to_pin_class);
VTR_ASSERT((*scratch).size() > 0);
*sink_rr = size_t((*scratch)[0]);
RRNodeId sink_rr_candidate = node_lookup.find_node(to_x, to_y, SINK, to_pin_class);
VTR_ASSERT(sink_rr_candidate);
*sink_rr = size_t(sink_rr_candidate);
}

return true;
Expand Down Expand Up @@ -1079,7 +1075,6 @@ void OverrideDelayModel::compute_override_delay_model(

//Look at all the direct connections that exist, and add overrides to delay model
auto& device_ctx = g_vpr_ctx.device();
std::vector<RRNodeId> scratch;
for (int idirect = 0; idirect < device_ctx.arch->num_directs; ++idirect) {
const t_direct_inf* direct = &device_ctx.arch->Directs[idirect];

Expand Down Expand Up @@ -1120,7 +1115,7 @@ void OverrideDelayModel::compute_override_delay_model(

int src_rr = OPEN;
int sink_rr = OPEN;
bool found_sample_points = find_direct_connect_sample_locations(direct, from_type, from_pin, from_pin_class, to_type, to_pin, to_pin_class, &src_rr, &sink_rr, &scratch);
bool found_sample_points = find_direct_connect_sample_locations(direct, from_type, from_pin, from_pin_class, to_type, to_pin, to_pin_class, &src_rr, &sink_rr);

if (!found_sample_points) {
++missing_instances;
Expand Down
12 changes: 6 additions & 6 deletions vpr/src/route/clock_connection_builders.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -74,18 +74,18 @@ void RoutingToClockConnection::create_switches(const ClockRRGraphBuilder& clock_
// Connect to x-channel wires
unsigned num_wires_x = x_wire_indices.size() * fc;
for (size_t i = 0; i < num_wires_x; i++) {
clock_graph.add_edge(rr_edges_to_create, size_t(x_wire_indices[i]), clock_index, arch_switch_idx);
clock_graph.add_edge(rr_edges_to_create, x_wire_indices[i], RRNodeId(clock_index), arch_switch_idx);
}

// Connect to y-channel wires
unsigned num_wires_y = y_wire_indices.size() * fc;
for (size_t i = 0; i < num_wires_y; i++) {
clock_graph.add_edge(rr_edges_to_create, size_t(y_wire_indices[i]), clock_index, arch_switch_idx);
clock_graph.add_edge(rr_edges_to_create, y_wire_indices[i], RRNodeId(clock_index), arch_switch_idx);
}

// Connect to virtual clock sink node
// used by the two stage router
clock_graph.add_edge(rr_edges_to_create, clock_index, size_t(virtual_clock_network_root_idx), arch_switch_idx);
clock_graph.add_edge(rr_edges_to_create, RRNodeId(clock_index), virtual_clock_network_root_idx, arch_switch_idx);
}
}

Expand All @@ -97,7 +97,7 @@ RRNodeId RoutingToClockConnection::create_virtual_clock_network_sink_node(int x,
RRNodeId node_index = RRNodeId(rr_graph.size() - 1);

//Determine the a valid PTC
std::vector<RRNodeId> nodes_at_loc = node_lookup.find_sink_nodes(x, y);
std::vector<RRNodeId> nodes_at_loc = node_lookup.find_grid_nodes_at_all_sides(x, y, SINK);

int max_ptc = 0;
for (RRNodeId inode : nodes_at_loc) {
Expand Down Expand Up @@ -204,7 +204,7 @@ void ClockToClockConneciton::create_switches(const ClockRRGraphBuilder& clock_gr
if (from_itter == from_rr_node_indices.end()) {
from_itter = from_rr_node_indices.begin();
}
clock_graph.add_edge(rr_edges_to_create, *from_itter, to_index, arch_switch_idx);
clock_graph.add_edge(rr_edges_to_create, RRNodeId(*from_itter), RRNodeId(to_index), arch_switch_idx);
from_itter++;
}
}
Expand Down Expand Up @@ -317,7 +317,7 @@ void ClockToPinsConnection::create_switches(const ClockRRGraphBuilder& clock_gra

//Create edges depending on Fc
for (size_t i = 0; i < clock_network_indices.size() * fc; i++) {
clock_graph.add_edge(rr_edges_to_create, clock_network_indices[i], size_t(clock_pin_node_idx), arch_switch_idx);
clock_graph.add_edge(rr_edges_to_create, RRNodeId(clock_network_indices[i]), RRNodeId(clock_pin_node_idx), arch_switch_idx);
}
}
}
Expand Down
8 changes: 4 additions & 4 deletions vpr/src/route/clock_network_builders.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -301,8 +301,8 @@ void ClockRib::create_rr_nodes_and_internal_edges_for_one_instance(ClockRRGraphB
clock_graph);

// connect drive point to each half rib using a directed switch
clock_graph.add_edge(rr_edges_to_create, drive_node_idx, left_node_idx, drive.switch_idx);
clock_graph.add_edge(rr_edges_to_create, drive_node_idx, right_node_idx, drive.switch_idx);
clock_graph.add_edge(rr_edges_to_create, RRNodeId(drive_node_idx), RRNodeId(left_node_idx), drive.switch_idx);
clock_graph.add_edge(rr_edges_to_create, RRNodeId(drive_node_idx), RRNodeId(right_node_idx), drive.switch_idx);
}
}
}
Expand Down Expand Up @@ -606,8 +606,8 @@ void ClockSpine::create_rr_nodes_and_internal_edges_for_one_instance(ClockRRGrap
clock_graph);

// connect drive point to each half spine using a directed switch
clock_graph.add_edge(rr_edges_to_create, drive_node_idx, left_node_idx, drive.switch_idx);
clock_graph.add_edge(rr_edges_to_create, drive_node_idx, right_node_idx, drive.switch_idx);
clock_graph.add_edge(rr_edges_to_create, RRNodeId(drive_node_idx), RRNodeId(left_node_idx), drive.switch_idx);
clock_graph.add_edge(rr_edges_to_create, RRNodeId(drive_node_idx), RRNodeId(right_node_idx), drive.switch_idx);
}
}
}
Expand Down
2 changes: 1 addition & 1 deletion vpr/src/route/connection_router.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -577,7 +577,7 @@ void ConnectionRouter<Heap>::timing_driven_add_to_heap(const t_conn_cost_params
if (rcv_path_manager.is_enabled() && current->path_data) {
next_ptr->path_data->path_rr = current->path_data->path_rr;
next_ptr->path_data->edge = current->path_data->edge;
next_ptr->path_data->path_rr.emplace_back(from_node);
next_ptr->path_data->path_rr.emplace_back(RRNodeId(from_node));
next_ptr->path_data->edge.emplace_back(from_edge);
}

Expand Down
14 changes: 3 additions & 11 deletions vpr/src/route/router_lookahead_map_utils.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -308,8 +308,6 @@ t_src_opin_delays compute_router_src_opin_lookahead() {

src_opin_delays.resize(device_ctx.physical_tile_types.size());

std::vector<int> rr_nodes_at_loc;

//We assume that the routing connectivity of each instance of a physical tile is the same,
//and so only measure one instance of each type
for (size_t itile = 0; itile < device_ctx.physical_tile_types.size(); ++itile) {
Expand All @@ -334,14 +332,8 @@ t_src_opin_delays compute_router_src_opin_lookahead() {

//VTR_LOG("Sampling %s at (%d,%d)\n", device_ctx.physical_tile_types[itile].name, sample_loc.x(), sample_loc.y());

rr_nodes_at_loc.clear();

get_rr_node_indices(device_ctx.rr_node_indices, sample_loc.x(), sample_loc.y(), rr_type, &rr_nodes_at_loc);
for (int inode : rr_nodes_at_loc) {
if (inode < 0) continue;

RRNodeId node_id(inode);

const std::vector<RRNodeId>& rr_nodes_at_loc = device_ctx.rr_graph.node_lookup().find_grid_nodes_at_all_sides(sample_loc.x(), sample_loc.y(), rr_type);
for (RRNodeId node_id : rr_nodes_at_loc) {
int ptc = rr_graph.node_ptc_num(node_id);

if (ptc >= int(src_opin_delays[itile].size())) {
Expand All @@ -355,7 +347,7 @@ t_src_opin_delays compute_router_src_opin_lookahead() {
if (src_opin_delays[itile][ptc].empty()) {
VTR_LOGV_DEBUG(f_router_debug, "Found no reachable wires from %s (%s) at (%d,%d)\n",
rr_node_typename[rr_type],
rr_node_arch_name(inode).c_str(),
rr_node_arch_name(size_t(node_id)).c_str(),
sample_loc.x(),
sample_loc.y());

Expand Down
8 changes: 5 additions & 3 deletions vpr/src/route/rr_edge.h
Original file line number Diff line number Diff line change
@@ -1,15 +1,17 @@
#ifndef RR_EDGE_H
#define RR_EDGE_H

#include "rr_graph_fwd.h"

/* TODO: MUST change the node id to RRNodeId before refactoring is finished! */
struct t_rr_edge_info {
t_rr_edge_info(int from, int to, short type) noexcept
t_rr_edge_info(RRNodeId from, RRNodeId to, short type) noexcept
: from_node(from)
, to_node(to)
, switch_type(type) {}

int from_node = OPEN;
int to_node = OPEN;
RRNodeId from_node = RRNodeId::INVALID();
RRNodeId to_node = RRNodeId::INVALID();
short switch_type = OPEN;

friend bool operator<(const t_rr_edge_info& lhs, const t_rr_edge_info& rhs) {
Expand Down
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